An Inverse Class E Power Amplifier with Finite DC-Feed Inductance

This article reports the design and experimental characterization of an inverse Class E power amplifier (PA) with a finite DC-feed inductance. The output matching network is designed to transform the standard circuit impedance to the optimum device matching impedance with inherent harmonic suppression characteristics. The inverse Class E PA achieves a peak drain efficiency of 70.6 percent and power added efficiency (PAE) of 67.2 percent, with a gain of 13.2 dB, while providing 40.7 dBm output power at 2.87 GHz. It can produce output power greater than 38.2 dBm with a drain efficiency better than 60 percent across a 250 MHz bandwidth.

The Class E power amplifier, introduced by N. Sokal and A. Sokal in 1975,¹ has become very popular at RF and microwave frequencies due to its simplicity and high efficiency. As the dual to the classical Class E PA, the inverse Class E PA has several advantages. First, it operates with a lower peak voltage, which relaxes the high breakdown voltage requirement of the active device. Second, the internal parasitic inductance of packaged devices can be absorbed by the series inductor in the inverse Class E topology.^2,3 There are some studies addressing this in the existing literature but almost all of the work assumes that the DC feed inductance has an infinite impedance.^2-8 In practice, however, it is impossible to realize an RF choke with infinite impedance at the fundamental frequency and its harmonic components. Moreover, using a finite DC-feed inductance has the advantage of minimizing size, cost and complexity of the overall circuit. The effect of a finite DC-feed inductance on the performance of an inverse Class E amplifier is analyzed and the design equations are given in references Mury et al⁹ and Hietakangas et al.¹⁰ An additional capacitor is introduced in Mury et al⁹ to resonate with the finite DC-feed inductance at the second harmonic frequency.

This article presents an inverse Class E PA with finite DC-feed inductance which is resonant with a part of the parallel circuit capacitance at the fundamental frequency. The finite DC-feed inductance is realized as a short-circuited shunt stub. Theoretical expressions are derived for the circuit elements and the analysis is verified through simulation. For experimental validation, an inverse Class E PA employing a gallium nitride (GaN) high electron mobility transistor (HEMT) device is fabricated and measured.

INVERSE CLASS E CIRCUIT DESIGN

Fundamental Theory

Figure 1(a) shows the ideal equivalent circuit of an inverse Class E PA with finite DC-feed inductance. It consists of an active device as an ideal switch, a series inductor (L₁), a parallel inductor (L₂), a shunt resonant circuit (L_pC_p) tuned to the operating frequency, a compensation capacitor (C) and a load resistance (R). This circuit is usually analyzed based on preliminary assumptions.⁴ The output voltage and current are sinusoidal and are defined as

where ω = 2 π f₀, f₀ is the fundamental frequency, V_R is the load voltage amplitude, φ is the initial phase, and G = 1/R is the load conductance.

From Figure 1 (b), it is seen that

When the switch is ON for 0 < ωt < π, the voltage on the switch is

At the same time, the current flowing through L₁ can be written as

When the switch is OFF for π < ωt < 2 π the current

As is the case with other Class E amplifiers, it is possible to eliminate power losses during ON-to-OFF transition by providing the following collector-current conditions:

Applying the zero-current condition in Equation 9 gives

where -π/2 < φ < π/2 because V_R > 0.

Applying the zero current-derivative condition of Equation 10 and using Equation 11 gives

and φ falls in the expected range for V_R > 0.

As a result, the steady-state switch-current waveform for 0 < ωt < π and the switch-voltage waveform for π < ωt < 2π  are

In the time domain, the switch current can be expressed in the form of a Fourier series as follows:

The DC supply current (I) can be found using Fourier transform equations and 4, 13 as

In an idealized inverse Class E mode of operation, there is no simultaneous nonzero voltage and current. That means that there is no power dissipation and the idealized collector efficiency is 100 percent. This implies that the DC power and fundamental output power are equal

By using Equations 11-16, and P_DC = I V_DD, the optimum value of L₁ and L₂ can be obtained as

At the fundamental frequency f₀, we can write 15 as

where a_i1 and b_i1 are de?ned as the Fourier coefficients of the switching current

The coefficients a_i1 and b_i1 are found using Equation 13 to be

On the other hand, from Figure 1 (b), it is evident that

Using Equations 2, 11, 12, 22, 25-30, R and C can be obtained as

The peak values of the switch voltage (V_swpk) and switch current (I_swpk)can be determined by differentiating the corresponding waveforms given by Equations 13 and 14 and setting the results equal to zero, thus obtaining

The optimum parameters are expressed as functions of a specific output power (P_out) and a given input DC voltage (V_DD) at a specified operating frequency (f_o) shown in Table 1. Table 1 also shows the optimum parameters of the classical inverse Class E topology.⁴

Comparison

In this section, the simulated example of a 500 mW, 5 V Class E PA, operating at 2.5 GHz and having 10 percent bandwidth (Q_LC = 10), is provided as a means to verify the theoretical analysis. The values of the circuit elements for topologies with infinite and finite DC feed inductance are presented in Table 2. These quantities are computed based on the equations in Table 2. The active device is modeled as a switch which has 0.01 Ohms ON resistance (used because the Advanced Design System (ADS) simulation algorithm of the switch component does not allow 0 Ohms ON resistance) and 10 kOhm OFF-state impedance. Simulation results are shown in Figure 2. A sinusoidal voltage is used to drive the switch model used in the ADS simulation in such a way that the switch duty cycle is 50 percent. From the voltage and current waveforms, it follows that the waveforms for the circuit modeled with a finite DC-feed almost coincide with the ones for the circuit modeled with an infinite DC-feed. Theoretical results of the inverse Class E amplifier with infinite versus finite DC-feed topology are also given in Table 3, and compared to the simulation results. From Table 3, it is evident that the theoretical analysis is in good agreement with the simulation results. The same efficiency has been obtained from both power amplifiers.

There are two advantages to using a finite DC-feed inductor (L₂) as opposed to using an infinite one. First is that the size and complexity of the overall circuit are minimized. For this design example, an extra inductor (L₂ = 5 nH) and a larger value of C (1.66 pF) are required for the inverse Class E topology with a finite DC-feed inductor (Table 3). Conversely, realizing a sufficiently high inductance to approach the infinite case would require greater circuit area. The second advantage is that the harmonic components are more thoroughly suppressed; resulting in higher output power and better drain efficiency. The parallel capacitance (C) can be divided into two parts; one part to compensate the phase angle error of the fundamental current, another to resonate with the finite DC-feed inductance at the fundamental frequency. The benefit of resonation at the fundamental frequency is better suppression at harmonic frequencies. This is indicated in the simulated results from Table 3 showing that the output power (464 mW) of the PA with finite DC-feed inductor is larger than the output power (462 mW) of the PA with the infinite DC-feed inductor.

Inverse Class E PA Using Transmission Line

For the experimental validation, a packaged GaN HEMT is used to replace the switch. The device cannot operate as an ideal switch due to the parasitic components caused by the package, interconnections and bond wires.⁶ Therefore, several internal parasitic components should be contained or compensated in the design procedure. Figure 1(c) depicts the proposed output equivalent circuit of the inverse Class E PA. The drain series inductance (L_d) is used as a part of L₁ in Figure 1(a). A series transmission line (TL_com) is used as the tuning line to provide additional inductance because the value of L_d extracted by the model in reference Cabral et al¹¹ is a little smaller than the optimum value of L₁ calculated using equation 1. Meanwhile, C_d simply represents the sum of all capacitance seen at the drain, and is compensated by a short-circuit shunt stub since the inverse Class E PA cannot deal with the output capacitance of the device.

Figure 3 shows the full schematic of the proposed inverse Class E PA. The finite DC-feed inductor (L2) is realized by a short-circuited shunt stub. The output network is designed to convert the standard 50 Ohm circuit impedance to an optimum matching impedance for the device of 83.9 Ohms using a simple L-type matching circuit. The lumped components are replaced by transmission lines using the Kuroda identity and the Richard transformation as explained in Mury et al.¹² The parallel capacitance (C) is replaced by four open-circuited shunt stubs that are deliberately designed to accommodate the 2^nd, 3^rd, 4^th and 5^th harmonic terminations, dispensing with the need for a series-tuned L_pC_p circuit as in Figure 1(a). The input of the device is conjugately matched at the frequency of operation. The values of R₁, R₂ and C₁ are obtained from the stability analysis based on S-parameter simulation in ADS.

FABRICATION AND MEASUREMENT

The proposed inverse Class E PA was designed and implemented using a 30-mil RO4350B substrate (ε_r = 3.5). The switching transistor is a Cree GaN HEMT power device (CGH40010F). Figure 4 shows the photograph of the fabricated amplifier.

Figure 5 shows the simulated and measured output power, drain efficiency, power-added efficiency (PAE) and gain of the proposed inverse Class E PA versus input power at 2.87 GHz. With the bias condition that V_GS = −3 V, I_DS = 50 mA and V_DD = 25 V, the peak drain efficiency and PAE of 70.6 percent and 67.2 percent with a power gain of 13.2 dB were obtained at an output power of 40.7 dBm. The power gain of over 15 dB is maintained over a wide output power range. The measured harmonic suppression for the 2^nd, 3^rd, 4^th and 5^th harmonics are 32.5, 45.6, 42.8 and 60.6 dBc. The measured values are lower than those obtained by simulation (52.7, 57.97, 54.55 and 69.9 dBc) because the measured frequency (2.87 GHz) is shifted from the design frequency (3 GHz). The frequency shift is due to inaccuracies in the large-signal model of the transistor, as well as fabrication tolerances associated with the substrate and surface-mount technology passive components.

Figure 6 shows the simulated and measured output power, drain efficiency and PAE versus drain bias voltage at an input power of 27.5 dBm. It is worth noting that a high efficiency of over 65 percent is maintained over wide range of drain bias voltages (13 to 30 V), because a flat efficiency response versus drain bias is required for drain voltage modulations such as envelope elimination and restoration (EER).⁶

Figure 7 shows the simulated and measured output power and efficiency as a function of operating frequency at an input power of 27.5 dBm. Output power of greater than 38.2 dBm and drain efficiency better than 60 percent are achieved over a 250 MHz bandwidth (from 2.75 to 3 GHz). Compared to other inverse Class E power amplifiers (Table 4), the proposed inverse Class E PA exhibits similar levels of efficiency and output power.

 

CONCLUSION

In this article, we described the design of a GaN-based PA using inverse Class E topology with finite inductance and harmonic suppression. The design equations are given to determine the values of circuit elements. The peak drain efficiency of 70.6 percent, PAE of 67.2 percent with a gain of 13.2 dB is achieved at an output power of 40.7 dBm at 2.87 GHz. The measured results demonstrate the validity and advantage of the proposed GaN HEMT inverse Class E PA when used as a solution for high-power transmitters requiring high efficiency.

ACKNOWLEDGMENT

This work was supported in part by the National Basic Research Program of China (973 Program, No. 2010CB327506) and the National Natural Science Foundation of China (No. 61040061) and the Project supported by Hunan Provincial Natural Science Foundation of China (No. 11JJ2034).

References

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