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Cascade Microtech Inc., a leader at enabling precision measurements of integrated circuits at the wafer level, and imec, a world-leading nanoelectronics research center, announced breakthroughs in probing stacked integrated circuits (3D-SICs), fueling an important growth engine for the semiconductor market. Through a Joint Development Agreement, Cascade Microtech partnered with imec to successfully probe 25 µm-diameter micro-bumps on a wide I/O test wafer with its fully-automated CM300 probe solution utilizing an advanced version of Pyramid Probe® technology. This achievement comes as part of imec’s 3D integration research program which includes other industry partners from the entire semiconductor value chain.
The 3D semiconductor market (including 3D-SIC, 2.5D interposer, and 3D WLCSP) is expected to represent 9% of the total semiconductor value by 2017, according to Yole Développement. Logic 3D SoC/SiP (including interposer chips, APE, CPU, FPGA, wide I/O memory, etc.) will be the biggest industry using 3D platforms in the next few years. 3D applications will emerge in high-performance computing, and electronic markets such as nanotechnology and medical applications, which will benefit from the high-density integration that 3D technology offers.
The semiconductor industry is exploring new methods to increase the functionality of ICs at a smaller footprint, extending Moore’s Law. 3D-SICs offer a solution to the speed, power and density requirements demanded by future mobile electronics platforms. Through-Silicon Vias (TSV) used in 3D-SICs shorten interconnects between logic elements, thus reducing power while increasing performance. Within imec’s 3D integration research program, industry leaders are jointly developing design, manufacturing, and test solutions to bring this new technology to high-volume manufacturing.
Cascade Microtech’s CM300 flexible on-wafer measurement system was designed to deliver superior positioning accuracy and repeatable contact, offering a level of precision that supports both shrinking pad sizes and pitch roadmaps. The CM300 captures the true electrical performance of devices with high-performance capabilities that include low leakage and low noise. As a comprehensive probing solution employing the latest advances in Pyramid Probe technology, the CM300 has proven to meet the fine-pitch (40 µm area array), low-force (< 1gf/tip) advanced probing requirements of 3D-SICs.
“We are excited that our work with Cascade Microtech has resulted in such a breakthrough. I believe together we’ve achieved a first in the industry,” said Erik Jan Marinissen, Principal Scientist at imec in Leuven, Belgium. “We are able to hit 25 µm-diameter micro-bumps with a high level of accuracy due to the probe-to-pad alignment features of Cascade Microtech’s CM300. And advances in their Pyramid Probe technology have enabled us to probe micro-bumped wafers with 40/50 µm pitch according to the JEDEC Wide-I/O Mobile DRAM standard.”
“Cascade Microtech’s CM300 probe solution is designed to provide greater alignment accuracy to probe directly on small, fragile micro-bumps. In conjunction with a fine-pitch, low-force Pyramid Probe card, we have achieved consistent, accurate measurements on a wide I/O test wafer using a single-channel, wide I/O probe core with an array of 6 x 50 tips at 40/50 µm pitch, with the ability to shrink down to 20 µm pitches in the future,” said Steve Harris, Executive Vice President, Engineering, Cascade Microtech. “Together, imec and Cascade Microtech are enabling the ongoing future of CMOS technologies through this ground-breaking work. 3D integration will undoubtedly result in increased performance and yield while reducing overall costs.”