The new Empire XCcel™ 3D EM field solver, to be released in October 2006, has been further optimized for speed. Utilizing modern processor architectures (for example, smart cache management), a speed-up of about 200 percent has recently been reported. Another speed-up has been obtained by using dual-core, single-CPU machines, the performance is at additional 60 percent, using dual-core, dual-CPUs, at least performance values of 350 Mcells/s have been achieved. Reference for the performance values was a modern 3.2 GHz dual-core, dual CPU desktop PC (Xeon), utilizing Empire XCcel there is neither a need for special hardware set-ups nor a limit for the application size to the memory space.
The highest performance figures have been achieved for a SPDT-MEMS switch consuming an overall main-memory of approximately 150 MB. The Xeon-PC used has a dual-core, dual-CPU architectures with on chip smart cache of 2 x 2 MB for each CPU. Of course, at very large memory sizes the bus interface to the main memory becomes the limiting factor in simulations.
The new Empire XCcel 3D EM field solver with a completely revised intuitive graphical user interface will be presented by IMST engineers. 3D editor, job control and post processing are integrated into one frame and simulations can be adapted from a large template library. A further speed-up of up 200% can be obtained by a smart cache management. New features include a broadband loss model, meta materials, spice parameter extraction and clipboard links of diagrams.