Software/EDA Channel

Analyst: Fully Integrated 3D EM Simulation

Analyst: Fully Integrated 3D EM Simulation

Analyst™ is a full featured, 3D electromagnetic (EM) industry-standard finite element method (FEM) simulator that is completely integrated into AWR’s Microwave Office™ circuit design environment (see Figure 1). It is the first software to give designers the ability to use 3D EM simulation when needed from within their circuit design software, without having to work in a third party/CAD drawing and simulation environment.

Analyst benefits those circuit designers who need to rely upon 3D FEM EM analysis for both the design and verification of their designs prior to manufacture. For RF/microwave designers of on-chip passive components, monolithic microwave integrated circuits (MMIC), microwave integrated circuits (MIC), RF printed circuit boards (PCB), modules and packaging, and hierarchical designs such as system-on-chip (SoC) and system-in-package (SiP), ease-of-use and minimal simulation setup time coupled with the elimination of manual drawing means maximum EM accuracy with minimal overhead.

3D EM Tool for the Practical Circuit Designer

Figure 1

Figure 1 Analyst is part of the AWR Design Environment™ integrated workflow.

The underlying philosophy of Analyst is to give the designer the power of 3D simulation in an easy-to-use circuit environment. This premise is made possible in two ways.

First, Analyst gives designers the ability to use 3D simulation in their normal design environment. Most circuit designs are planar, whether developed for ICs, modules or boards; consequently, 3D EM simulators are really only needed in the few places where planar EM simulators are not practical, for example, a gap in the dielectric substrate from a recessed chip on a board. Therefore, it makes complete sense to provide 3D EM simulation capabilities directly and seamlessly within a circuit design environment.

Second, Analyst comes preconfigured with settings (boundary, ports, mesh, modes) that are tailored to the class of problems specific to these IC, module, and board designs. Prior to Analyst, designers had to define, specify, and ship their 3D problems to an external EM tool, set up and simulate them, and then import the results back into their circuit environment. The first issue with this method is one of time and potential error in carrying out the export/import of the project. The second is that these simulators require many esoteric settings of ports and solver options that the average designer can feel uncomfortable with and overwhelmed by and therefore less confident with the end result. In the Analyst approach, the settings are already optimized for the typical problems designers are likely to encounter, therefore the manual interactions are minimized, reducing potential user error and increasing confidence in results.

Analyst in the Design Flow

Figure 2

Figure 2 Analyst automatically generates parameter controlled layout cells (Pcells).

Microwave Office has traditionally given designers the flexibility to easily use EM simulation in a variety of ways. This use model has been evolving for a number of years, including the concept of extraction, where the layout can be automatically selected, EM simulated, and the results included into the circuit.

AWR continues to improve the functionality of the EM environment (Extraction flow/EXTRACT block) within Microwave Office by now offering 3D FEM EM analysis via Analyst.  Even before Analyst, layouts could be controlled by variables, allowing the creation of models with swept parameters. For example, a custom model of a discontinuity like a notched tee is easy to create. Designers can tune the parameters of the model, and can even run optimizations. Layouts can also take advantage of preconfigured layout cells (Pcells), as shown in Figure 2, the shapes of which are controlled by parameters.  And now with Analyst, the EM environment has been enhanced to handle 3D structures common to planar circuit topologies.  For example, Pcells now automatically create 3D bond wires, ball grid arrays (BGA), tapered vias, and bond straps. Common 3D discontinuities like finite sized dielectric bricks and package walls can also be easily included.

Real-world Chip/Package/Board Example

The key advantage of Analyst is its tight integration within AWR’s Microwave Office circuit design and simulation environment. To demonstrate the real-world value of this unique feature, let’s look at an example: the optimization of a board-to-module-to-chip signal path.

Figure 3

Figure 3 The performance of the transition from Port 1 on the board to Port 2 on the chip is analyzed.

Figure 4

Figure 4 The return loss is shown from 10 to 20 GHz before optimization.

Figure 3 shows the board, module and periphery of the chip being investigated. The signal goes from Port 1 on a trace on a PC board, onto a module by means of a BGA, along a trace on top of the module, and over to Port 2 on the chip by means of a bond wire. The design goal is to have a return loss of better than 20 dB over the frequency range of interest, 10 to 20 GHz.

Analyst simulation results, shown in Figure 4, for the layout of the product photo indicate that the design goal is not yet being met. To remedy this, Analyst is used within the Microwave Office design environment to enable easy design optimization via a three-stage approach:

  • Isolate specific area(s)
  • Identify electrically their behavior
  • Modify the layout to bring behavior into spec

Figure 5

Figure 5 The entire signal path is simulated — the return loss meets the specification of being less than 20 dB over the desired frequency range.

Analyst has a number of features that designers can take advantage of as the design is modified. The tool has the ability to simulate only portions of the layout, thereby reducing problem size and increasing simulation flexibility (Step 1). The Analyst results are inserted into a schematic, capacitors are attached to the ports, and their values tuned and optimized (Step 2). The layout is then augmented to give the desired extra capacitance or inductance (Step 3). Again, only the portion of the layout of interest is simulated. In this manner, Analyst has been designed to minimize the amount of setup time required for a simulation. The final solution that results from this three-stage approach is one in which the bond wire has been doubled and shortened to reduce inductance, the gap between the bond wire pad and side grounds has been decreased to increase capacitance, and the ground vias on the board have been moved away from the ground balls to increase the loop inductance and compensate for the ball capacitance. The entire structure is then simulated as a final verification check to ensure the design meets with success. The resulting data is shown in Figure 5.

Analyst Applications

Analyst is specifically designed with the knowledge that RF/microwave designers need to perform analysis on interconnects commonly found within high-frequency packages, boards and modules.

  • Die-level interconnect: Analyst enables designers to simulate and accurately capture the electrical behavior resulting from die-level interconnects (see Figure 6) such as air bridges, spiral inductors, capacitors and tapered vias within gallium arsenide (GaAs), gallium nitride (GaN), silicon germanium (SiGe), or bipolar junction complementary metal oxide semiconductor (BiCMOS) ICs so that IC design performance can be fully optimized.
  • IC/package/board/module interconnect:  Analyst is equally capable of solving the challenges of IC packaging and chip/package/board and module interconnect (see Figure 7) that include bond wires, bumps, ribbons and/or solder balls.  Analyst accurately accounts for each interconnect and its associated parasitics.

Figure 6

Figure 6 Die-level interconnect.

Figure 7

Figure 7 IC/package/board interconnect.

Electromagnetic simulators are commonly used to help designers gain a more accurate understanding of the physical layout and interconnect common to ICs, PCBs, modules and associated packaging. The main advantage of Analyst is its tight integration into the AWR Microwave Office circuit design environment. With Analyst seamlessly embedded into the Microwave Office environment, circuit designers save time (fewer mouse clicks and menu options) while gaining greater EM-insight into design performance. For example, layout setup and drawing are simplified by preconfigured 3D Pcells for the bond wires and BGA balls. Hierarchy is supported in the EM layout, making for easier design reuse. Tuning, optimization and sensitivity and yield analysis can be quickly implemented through the use of parameterized layout, without having to leave the Microwave Office environment. Since Analyst is optimized for RF and microwave designers, the designer is not required to become an expert on EM simulation software settings. It is now possible to seamlessly include 3D EM simulation in critical circuit simulations such as optimization, tuning of circuits like filters, sensitivity and yield analysis, and even nonlinear circuit simulation using harmonic balance. The designer can fully concentrate on his/her design, easily using 3D EM simulation when needed, without having to spend time learning a complex EM point tool. The key point is that designers can now focus more of their time on circuit designs/behavior and less on the nuances of using a 3D EM point tool.

AWR Corp.,
El Segundo, CA,

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