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Aerospace and Defense Channel / Cellular 4G/LTE Channel / Test and Measurement Channel / RFID/GPS/Location Channel

E/D GaAs PHEMT Core Chips for Electronically Steerable Antennas

November 14, 2012
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Despite great progress in silicon-based microwave integrated circuits, III/V technologies continue to demonstrate improved capabilities, offering optimum trade-offs in terms of noise figure (NF), gain, power and linearity for various applications, including wireless telecommunication infrastructure, security scanners, radars and instrumentation. Historically, a weakness of III/V technologies has been their limited level of integration. This article demonstrates how E/D PHEMT processes now facilitate analog functions like phase shifters and attenuators, with state-of-the-art performance, on the same chip as digital control functions, such as serial to parallel converters to produce highly integrated Core Chips for electronically steerable antennas – from C- to Ka-Band today and even E-Band in the near future.

Due to higher electron mobility and velocity, III/V technologies provide higher frequency cut-off Ft, Fmaxand also lower noise and higher gain than silicon RFICs. The wide bandgap produces higher breakdown voltage (Vb), higher power and better linearity. The Fmax ×Vbproduct is between two and five times better than that of silicon, which means high power at high frequency. Examples include 4 W power amplifiers up to 31 GHz, low noise amplifiers from 75 to 110 GHz and 2.8 dB noise figure.

At first sight, this leading-edge performance only seems possible for single-functions, such as power amplifiers or low noise amplifiers, with no digital circuitry, like digital phase shifters or digital attenuators, on the chip. However, the example of Core Chips for electronically steerable antennas will be used to show that III/V processes are not limited to high performance simple single-functions.

Figure 1

Figure 1 Phased array antenna principle.

Electronically steerable antennas are widely used in both military and civilian applications, such as military radar, earth observation equipment for satellites, radio astronomy and mobile radio. These antennas avoid the noise, reliability and maintenance issues of mechanically steerable systems, by receiving and/or transmitting using a matrix of independently parameterized radiating elements to form a directed beam. The orientation of the beam is obtained by the use of variable phase shifters attached to each radiating element (see Figure 1 and the associated equation).

The side lobes of the beam may then be controlled by variable attenuators also linked to each radiating element. As the same antenna is often used for transmission and reception, each radiating element may be linked to a power amplifier, a low noise amplifier and some T/R switches. This makes at least six circuits per radiating element and the number of elements per antenna can easily be several thousand.

Figure 2

Figure 2 SIPO cell based on D-mode transistors.

Small, cost-effective solutions must have high levels of RF integration, but comprehensive digital control of each element is vital. The concept of the Core Chip was introduced to integrate all these functions in a single chip at reduced complexity and cost, to allow electronically steerable antennas to address both high-end and low-end markets.

So, a Core Chip is a complete control function for electrically steerable antennas with phase shifters, attenuators, switches, low noise amplifiers and medium power amplifiers, on the same chip as their digital control circuits. Such multifunction microwave circuits are very challenging – they must minimize noise in Rx mode, maximize amplifier gain in Tx mode, and at the same time compensate losses in phase shifters, attenuators and switches that vary by as much as 15 dB. This is where III-V PHEMT technology has an advantage over silicon by combining high gain and low noise at high frequency, with an extremely limited DC consumption (hundreds of mW).

The need for digital control of all these analog functions also brings a considerable interconnection problem. For high resolution, twelve bit accuracy, a circuit may need up to 24 pads, with a large number of control lines routed across the chip so that the digital switching signals do not interfere with the analog RF functions. For an antenna with thousands of radiating elements, this is hardly feasible. Integrating a digital Serial Input Parallel Output (SIPO) converter block directly on to the Core Chip is a cost effective solution, which reduces a maze of interconnection to one serial data input.

Figure 3

Figure 3 SIPO cell based on E-mode transistors (a) and comparison between D-mode and E-mode transistors DC characteristics (b).

One way to design a SIPO is to use only some depletion mode transistors for power functions and digital control functions as depicted in Figure 2. However, the complexity of the SIPO structure and particularly the transistor voltage supply present problems. As shown in the figure, the biasing of gates must be done using a negative voltage supply and DC level shifting using diodes. This complicates the structure and substantially increases the area the SIPO occupies on the chip. Depletion mode transistors are well suited for power and noise performance, but enhancement mode transistors provide a much more efficient SIPO design for on-chip integration.

The structure of an enhancement mode SIPO block is depicted in Figure 3. Unlike depletion mode transistors, enhancement mode transistors are pinched off at a gate voltage of
0 V and deliver current while the gate voltage supply is positive. One advantage of this is called “direct coupling,” where the second stage gate voltage supply can be fed by the first stage drain voltage supply. A second advantage is the low consumption due to low knee voltage of enhancement mode transistors.

One of the enhancement/depletion processes, suitable for highly integrated Core Chips for steerable antennas, is composed of enhancement and depletion transistors with Ftapproximately 60 GHz, making it a good candidate for single-chip integration of digital circuits, such as SIPOs, low noise amplifiers, medium power amplifiers (20 dBm and above) and several on-chip switches. As an example, Figure 4 shows a 26-bit SIPO using 1200 enhancement transistors which is only 46 transistors per bit. This consumes an exceptionally low overall power of 60 mW (2.3 mW/bit).

Figure 4

Figure 4 Die photography of a 26 bit SIPO.

Figure 5

Figure 5 Die photography of a DC regulation block.

For an antenna comprising hundreds or thousands of elements, DC consumption for each Core Chip must be as low as possible. On-chip DC regulation, using an E/D GaAs PHEMT process, helps to minimize the overall mmW/bit, process deviation effects, reduce design margins (layout corners) and also reduce system complexity, since no tuning is necessary. So if the voltage supplies are not well regulated in the user’s system, the on-chip DC regulation, as shown in Figure 5, enables Core Chips across normal process variations to work in optimum conditions of noise, gain and phase and attenuation consistency.

Figure 6

Figure 6 Die photography of a C-Band 6-bit core chip.

Core Chips are already used in several applications such as space systems in C-Band, civilian Internet by satellite in X- and Ku-Bands and military missile guidance in Ka-Band. Some real-world examples are highlighted below.

The first 5.4 GHz chip1 integrates a 6-bit digital phase shifter (2.5° rms error over 4096 states), a 6 bit digital attenuator (0.25 dB rms error over 4096 states), six switches, a 12-bit SIPO and amplifiers with DC regulation providing 20 dBm of output P1dB. The overall die is shown in Figure 6, and the dashed lines highlight each function embedded on the chip.

The topology of the chip is arranged to separate the phase shifters and attenuators with SIPO in the middle. These two areas are also separated by the ground wall. This avoids phase distortions at high attenuation states due to coupling between RF input and output. Such design rules are a trade-off between chip size (and cost) and electrical performance such as very low phase and amplitude rms error over all states.

The second example shows a high volume civilian application, a broadband Internet by satellite for cars or planes, which have a phased array antenna on the roof.2A single antenna includes 150 Core Chips. Without such a highly integrated single chip, the larger size, mounting and routing of each element and higher cost would make such an antenna impossible.

In this example, a single chip integrates a 4-bit phase shifter (180°, 90°, 45° and 22.5°) cascaded with a two-stage low noise amplifier and a SIPO. Since this antenna only operates in Rx mode, this example does not integrate switches and medium power amplifiers. High integration reduces space, complexity and overall cost.

Figure 7

Figure 7 Ka-Band core chip phase and attenuation control response.

The third example highlights the capability to design and use Core Chips in E/D processes, up to Ka-Band (34 to 36 GHz) and at Ft/2 of the process. As previous examples, this Core Chip is composed of phase shifters, attenuators, a 12-bit serial to parallel converter and a low noise amplifier (noise factor below 8 dB in reception mode). Unlike the previous example, this chip also includes a medium power amplifier (P1dB of 10 dBm), with less than 350 mW consumption.

Figure 7 shows the phase and attenuation control of the chip over the 34 to 36 GHz band. Note the flatness of phase and attenuation over the bandwidth. This characteristic is mandatory for electronically steerable antennas. If the phase is not constant across the overall bandwidth, then pointing the beam in the same direction at different frequencies would demand dynamic phase changing for each radiating element, depending on the frequency.

This would make the system far too complex and would effectively close the door to large bandwidth applications. In fact, each Core Chip in this antenna array is programmed with a phase value, so the combination of each single radiating element points the overall beam in one precise direction.

While using a phase shifter, it is common to give 15 percent of bandwidth as a maximum value of use range. As an example, at 35 GHz, the maximum bandwidth will be approximately 5 GHz. At Ka-Band, the phase shifter response, from 30 to 40 GHz (see Figure 7), exhibits a phase deviation of 20°, whereas between 32.5 and 37.5 GHz the deviation is less than 5°, which is the smallest phase shifting step. When the beam pointing error due to phase steering is smaller than half the antenna beam width, then the phase shifters cannot be used anymore.

To achieve higher beam pointing accuracy, True Time Delay (TTD) functions are a solution.3Instead of changing the phase of each radiating element, the trick is to change the true time delay between each radiating element to obtain the same differential phase shifting between two elements, whatever the frequency. A constant time delay on a large bandwidth is possible using different lengths of switched lines, since phase variation is proportional to frequency. Switches can be used to modify the overall line length.

A 5-bit TTD has five different line lengths making possible 64 different length combinations and 64 different time delays. Figure 8 shows a 5-bit true time delay chip and its performance from 6 to 18 GHz. One can see the five delay line blocks with increasing lengths that are combined under digital control. The graph highlights the flat behavior over a wide frequency range.

Figure 8

Figure 8 6 to 18 GHz 5-bit True Time Delay Chip measured results.

The III/V process nevertheless limits the range of frequencies that Core Chips can operate over. To develop Core Chips with on-chip SIPO control to work at 60 GHz and up to E-Band, designers must use a process with an Ftof approximately 200 GHz. A 100 nm true E-mode process, using a metamorphic layer,4will be available next year. It offers an Ftof 200 GHz and Fmaxof 300 GHz, which unlocks the technology for Core Chips up to 100 GHz.

This device provides enough RF power and performance, even using only enhancement mode transistors. The maximum stable gain of one stage at 30 GHz is 15 dB, showing that
E-mode gain is no longer an issue even at these higher frequencies. The large average gate voltage swing of 0.62 V and the 100 mV threshold voltage also supports the integration of switches.

In conclusion, it can be said that E/D III/V processes enable the integration of high performance amplifiers, phase shifters and attenuators, on the same chips with serial to parallel converters, to achieve state-of-the-art Core Chips. This level of high performance integration makes the implementation of large electronically steerable flat antennas possible at minimum cost and size, from C-Band to Ka-Band, today, and at E-Band in the near future.

References

1. R. Giordani et al., “Highly Integrated and Solderless LTCC Based C-Band T/R Module,” 2010 European Microwave Conference Proceedings, pp. 902-905.

2. G. Langgartner et al., “Dedicated GaAs Core Chip for Mobile Satellite Ku-Band Front Ends,” 2010 ESA Conference.

3. F.E. van Vliet et al., “Fully-integrated Wideband TTD Core Chip with Serial Control,” 2003 GAAS Applications Symposium Digest, pp. 89-92.

4. H. Maher et al., “A 200 GHz True E-Mode Low-Noise MHEMT,” IEEE Transactions on Electron Devices, Vol. 54, No. 7, July 2007, pp. 1626-1632.

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