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Industry News / Semiconductors / Integrated Circuits

STMicroelectronics and Soitec make 28 nm FD-SOI CMOS process available

October 22, 2012

STMicroelectronics, Soitec (Euronext) and Circuits Multi Projets®(CMP) announced that ST’s CMOS 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses innovative silicon substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as it nears completion of its first commercial wafers.

The introduction in CMP’s catalogue of ST’s 28 nm FD-SOI CMOS process builds on the successful collaboration that has allowed universities and design firms to access previous CMOS generations. Since CMP started offering the ST 28 nm CMOS bulk technology in 2011, some 60 universities and microelectronics companies have received the design rules and design kits and 16 ICs have already been manufactured.

“There has been a great interest in designing ICs using these processes, with about 300 projects having been designed in 90 nm (phased out in 2009), and more than 300 already in bulk 65 nm,” said Bernard Courtois, Director of CMP. “In addition, more than 60 projects have already been designed in 65 nm SOI and it is interesting to note that many top universities in Europe, USA/Canada and Asia have already taken advantage of the collaboration between CMP and ST.”

The CMP multi-project wafer service allows organizations to obtain small quantities--typically from a few dozen to a few thousand units of advanced ICs. The cost of the 28 nm FD-SOI CMOS process has been fixed at €18,000 per mm2, with a minimum of 1 mm2.

“With the first designs in FD-SOI technology already in the pipeline, the time is right to make the technology available to the research communities. Our FD-SOI manufacturing process allows existing designs to be quickly and easily ported to FD-SOI where significant power and performance benefit can be realized,” said Philippe Magarshack, Executive Vice President, Design Enablement and Services, STMicroelectronics. “In addition, ensuring that universities have access to our leading-edge technologies can help us attract the best young engineers as part of our commitment to remain a technology leader on a long-term basis.”

“Our partnership with STMicroelectronics and CMP is an additional example of Soitec’s commitment to providing differentiated materials solutions to the open market, supporting the continual expansion of the FD-SOI ecosystem and users of advanced technologies,” said Steve Longoria, senior vice president of worldwide strategic business development for Soitec. “Through this partnership we will see new and innovative products based on Soitec's FD-SOI materials, as a result of providing universities and other customers with a proven path for developing and testing next-generation integrated circuits.”

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