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Cellular 4G/LTE Channel / Industry News

RFEL stretches the dynamic range of ADCs to provide 'Best in Class' product performance

October 5, 2012
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RFEL, which specialize in high performance electronic signal processing solutions, has produced a solution to overcome the common performance bottleneck of the dynamic range of high speed ADCs that can prevent innovative projects in wireless communications and instrumentation from getting off the ground. RFEL has successfully extended the dynamic range of an 8 bit 800MSPS ADC from 52 dB up to 74 dB (see figure) in order to meet specific customer requirements for an industrial test product design.

Increased Dynamic Range of ADCs 

Dr. Alex Kuhrt, RFEL's CEO, explained, "Our many man-years of leading-edge, signal processing design knowledge enabled us to really push the envelope of the ADCs' dynamic range so that the customer could get a new product on the market that has 'best in class' performance. Breaking through the dynamic range limit of the ADCs was just one of the design challenges for this project, which is one of the growing number of complete box solutions that we are providing as part of our Design Services operation. RFEL was responsible for the entire design flow from initial concepts and algorithms through to PCB layout, design of firmware, software, mechanical housing, and final environmental and EMC testing."

The ADCs were supplied by e2V and Francis Jones, e2V's Business Development Manager, commented, "We are delighted to see our devices being used in such an innovative way to extend their dynamic range. It is impressive to see just how much additional performance can be achieved by using our device."

The multi-channel analogue and digital design uses six, quad speed, EV8AQ160 ADCs, two 1.6 GHz PLLs, four high speed FPGAs and a processor. The complexity of integrating multiple large BGA devices and associated high speed I/O into a small area required a 14-layer PCB design. The added signal sensitivity requirement necessitated linear power supply regulators, low noise analogue components and careful layout of power planes. Analogue simulation was used to prove the stability and frequency response of the input chain whilst the RTL design was checked against a bit true Matlab model.

The dynamic range of the ADC was extended by employing a stacked ADC architecture. This approach provides large gains in dynamic range by use of parallel data capture paths with staggered attenuation settings. Matching the frequency, phase and amplitude characteristics on these parallel paths is critical to a successful implementation. Therefore special attention was focused on the architecture of the analogue design to mitigate potential mismatch of device characteristics.

After the received signal has been converted to the digital domain, the input data rate for each channel is 29Gb/s. Initial signal processing reduces the rate whilst maintaining full timing precision. Further time and frequency domain measurements are applied before passing results on to the processor. Software handles final adjustments to the data and manages the user interface. A network connection allows control, data transfer and updates to be carried out via remote access. 

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