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Software/EDA Channel

Proper Stack-Up in a Multilayer PCB to Reduce Noise Coupling and Improve EMI

February 14, 2012
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As digital circuits became faster, direct coupling among power planes in multilayer printed circuit boards (PCB) became a major concern for signal integrity/power integrity and electromagnetic interference (EMI). Fast signals produce electromagnetic waves that can propagate by means of the parallel plates in the PCB, induce noise on the signals passing through the power bus (vias) and radiate from the edge of the board. The present study focuses on the analysis of the noise that propagates from a power plane to another power plane due to their proximity. To mitigate this problem, proper design of both power and ground planes in the stack-up is illustrated. A test board is fabricated and measurements are performed in order to validate the numerical electromagnetic model.

With the ever-increasing speed and density of a digital integrated circuit system, the effects due to field interaction among IC chips, packages and PCBs have become more and more the limiting factors in high-speed system design.1 Signal and power integrity (SI/PI) effects, such as propagation delay, crosstalk and simultaneous switching noise (SSN), require accurate and efficient electromagnetic analysis and modeling beyond the traditional static methods with a few lumped circuit elements.

Modeling a power plane, using equivalent lumped inductors2 or inductive networks, can give erroneous results for computing power supply noise, because the model may only take into account the effect of slower current transient. Moreover, in many methods that have been applied in the past to analyze multilayered power distribution networks (PDN) containing several planes, the plane-pair have always been assumed to be isolated from each other. A method for analyzing the field penetration in package power distribution networks is proposed3 but also, in this case only, coupling of power/ground (PWR/GND) planes is studied. The importance of the topic is confirmed by recent publications focused on the modeling of PWR/GND planes and PDN in multilayer PCBs.4,5

On modern high performance digital circuits, the energy increases and is provided by PWR planes embedded in the multilayer structure of the PCB. These PWR planes can induce noise causing SI problems for drivers/receivers mounted on the board and power supply noise during input/output (I/O) switching. This last aspect often causes voltage fluctuations and circuit delay due to the transient currents injected into the PDN.

Decoupling capacitors connected to the PWR/GND leads are added to mitigate the effect of SSN; they help to stabilize the power distribution bus by supplying current that opposes any change in the power bus voltage. On the other hand, it has been demonstrated that all noise mitigation techniques that employ discrete capacitor components have a fundamental limitation, due to the inherent inductance arising from the leads of the capacitor.6 Conventional PWR planes structures should be treated as dynamic electromagnetic systems in which waves can propagate between the PWR/GND planes. For this reason, a full wave modeling, which includes the vias, connectors and all the planes, is necessary to adequately detail the effects that are necessary to quantify the PCB from a SI and EMI point of view. This article investigates the effect of noise propagation in a multilayer PCB, due to the close proximity of two PWR planes and provides an overview on the design of the power bus location on multilayer PCBs

Test Structure and Model to Hardware Validation

The test board used for this study is illustrated in Figure 1. It is an eight layer board of total thickness t = 2.088 mm and the dimensions are 260 × 210 mm; the dielectric material is standard FR-4 with nominal relative electric permittivity, εr = 4.5 and loss tangent, tgδ = 0.02 at 1 GHz. The conductor is copper with conductivity σc = 5.5×107 S/m and the thickness of all the PWR/GND planes is 0.018 mm. Four SMA connectors, named respectively A1, A, B1 and B, are mounted on the top plane of the board in order to perform S-parameter measurements. SMA A1 and B1 are connected to the power plane PWR1. SMA A and B are soldered on the power plane named PWR2. PWR1 and PWR2 are two power planes, which are located in the stack-up one next to the other and separated by a 0.72 mm dielectric thickness. S-parameters are measured between SMA A1 and SMA B1 with an Anritsu 37247C vector network analyzer (VNA) and a full two-port calibration has been made at the ends of the probes.

2M30F1abx250.jpg

Figure 1 Fabricated test board used for the model to hardware correlation (a) and stack-up of the PCB (b).

2M30F2x250.jpg

Figure 2 S21 correlation between measured and simulated results (A1-B1).

A full wave field solver CST STUDIO SUITE®, based on the finite integration technique (FIT)7, is employed to calculate S21 between A1 and B1 on the same test board and the calculated results are compared with the measurements, as shown in Figure 2. In the equivalent electromagnetic model, it is important to point out that the SMA connectors are also modeled and particular attention has been given to the excitation: the two ports at which the S-parameters are evaluated are the upper surface of the SMA A1 and SMA B1. In order to ensure a TEM structure of the electromagnetic field (essential condition for a meaningful interpretation of the scattering matrix) the TEM excitation has been realized by considering waveguide ports at the top of the SMA.

Good agreement can be observed between the measured and the numerically calculated data. The considered frequency range is 20 MHz to 2 GHz, which is a typical value used for PI analysis. The small difference in the amplitude of the measured and simulated S21 is due to the fact that, in the actual board, there are multiple vias with different diameters, which subtract useful area to the PWR/GND plane pair, therefore increasing the S21. Figure 3 shows S21 on the PWR2 due to a wave propagating on PWR1 (B-A1). It can be noted that the magnitude is only about 10 times attenuated with respect to the original wave on PWR1 and this value is certainly not enough to guarantee a good SI immunity. To confirm this, Figure 4 is a picture of the current field distribution on a cross section of the board calculated at 1 GHz, which shows the amount of current on the other PWR plane, causing coupling with it. This phenomenon is due to the fact that the two PWRs are separated by only 710 μm of dielectric material.

2M30F3x250.jpg

Figure 3 S21 correlation between measured and simulated results (B-A1).

2M30F4x300.jpg

Figure 4 Current distribution at 1 GHz in the cross section of the considered board stack-up.

This is not the worst case scenario.As in realistic high speed PCBs, the coupling effect is more accentuated, due to the presence of multiple antipads and islands, which are necessary to design through/buried vias as well as to isolate the sensitive circuitry parts. As seen in Figures 2 and 3, the size and shape of the board introduce few resonant frequencies whose amplitude can be, in principle, reduced by using a thinner dielectric material between the two planes. In particular, the reduction of the amplitude in dB is proportional to the ratio between the two layers and the S21 decreases according to the quality factor of the cavity formed by them. The quality factor, determined by the total loss and the energy storage is linearly dependent on the height of the cavity formed by the two metal layers. Although S-parameters are evaluated, the general S-parameter matrix can be simply transformed into the impedance matrix using the following equation:

2M30M1x250.jpg

[I] is the identity matrix and Z0 is the characteristic impedance of the network analyzer. The transfer impedance Z21 on the off diagonal of the impedance matrix, gives indications about the open circuit voltage at a victim location on the power bus generated by the current injected at a source location. From Equation 1, if the following conditions are fulfilled,

2M30M2abx250.jpg

as it normally happens for a PWR/GND plane pair, the magnitude of Z21 is related to the S21 measurements as the following:

 

2M30M3x250.jpg

Consequently S21 simulations and/or measurements can be used to study the transfer impedance between two selected points’ places on the power bus.

Due to the CPU time, when performing full-wave analysis, alternative methods can be employed to evaluate the noise coupling among multiple points on a PCB. If the PWR/GND layers have a rectangular shape, the resonant frequencies for the TMnm modes are given by the equation:

2M30M4x250.jpg

2M30F5x250.jpg

Figure 5 Modified stack-up (a) and comparison of S21 magnitude with the modified stack-up (b).

where m and n are the mode number, L is the length of the board, W is the width and εr is the relative permittivity of the dielectric between the plane, and c is the speed of the light in free space. The resonances of the frequencies where the measured S21 levels reach their peaks (see Figures 2 and 3) match almost perfectly with the frequencies calculated with Equation 4.

Noise Propagation Reduction by Modifying the Stack-up

In this section, it is demonstrated how the changing of the location for the plane PWR1 as far as shown in Figure 5 will allow it to drastically reduce the effect of coupling between the two PWR planes. From the transmission coefficient S21, which can be measured or calculated on PWR2 when a wave propagates on the other, it is evident how, in this case, the reduction is approximately four to five times, with respect to the previously examined case. This situation allows it to ensure an efficient isolation level between the two PWR planes, when a wave propagates on one. The value of the S21 magnitude, calculated by means of the FIT code when PWR1 is located between the TOP plane and a GND plane, is compared with the results obtained between SMA B1 and SMA A of the original stack-up.

The advantage of this concept is that without any additional metal layer the coupling between the two PWR planes is reduced to extremely small values. However, in some cases, a minimum number of layer and position in the stack-up is required in order to maintain the PCB functionality. In such cases, an extra metal layer is required to guarantee a lower coupling level, which unfortunately introduces extra costs. Alternative solutions can be obtained by introducing effective power islands8 and shorting vias, which provide some isolation among the layer or more advanced filtering structures, such as two-dimensional (2D) electromagnetic bandgap structures (EBG)9 or new techniques based on photonics crystals.10

EMC/EMI Analysis

The EMC/EMI of the proposed test board is also investigated. Figure 6 shows the absolute radiated emission at 3 and 10 m away from the board when an input current Inoise = 1 mA is used to inject noise in the position A1. To understand whether the GND plane via stitching, placed around the board edges, has any effect with respect to the EMI produced by the fringing fields on the power bus, a new board is designed. It assumes the presence of stitching vias among the layers at the periphery of the board, 5 mm distant from the edge and with a pitch value of 6 mm. The emission profile is calculated and compared to the original board and the results are illustrated.

2M30F6x250.jpg

Figure 6 EMI emission for original (EMC [1]) and modified stack-up (EMC[1]_1) at a distance of 3 m (a) and 10 m (b).

2M30F7abcdx250.jpg

Figure 7 Surface current distribution at 1 GHz on the PWR1 and fringing field of the H-field for original PCB (a, b) and PCB with stitching vias (c, d).

It can be observed that the 3 m radiated field is below the FCC level up to 1.4 GHz, which represents a substantial improvement with respect to the case of the original board without stitching vias. The radiated emissions at 10 m are even lower and below the FCC levels over the whole frequency range of interest 0 to 2 GHz. The presence of the board ground ring represented by the stitching vias also provides protection against ESD generated during the board handling; therefore, it serves two purposes. Figure 7 confirms the additional coupling on PWR1, when no stiching vias are present as well as the strong fringing field predicted at the edge of the board, which causes increased emissions. By adding the ring of stitching vias, both noise coupling (represented by the lower value of the surface current on the PWR1) and the fringing field are consistently reduced.

Conclusion

A GND-PWR1-PRW2-GND board stack-up is studied from both a PI and SI point of view. Numerical simulations, validated by means of measurements on a given test board, demonstrate that the PWR planes location in multilayer PCBs can be very important. Both experimentally and numerically calculated results have pointed out that when two PWR planes are too close, there is excessive coupling between them and this generates a propagation of noise on one PWR plane when the other is excited. The concept is also shown by means of current distribution on the board planes. This can be avoided by changing the PWR plane location and realizing a different stack-up. Using PWR layers, sandwiched between GND layers stitched together, has beneficial effects on the board signal integrity due to a more stable reference offered to the signal paths. The radiated emissions of the board are also studied and it is demonstrated how the electrostatic ring placed all around the board can significantly decrease the maximum value of field radiated from the edge of the board.

References

  1. M. Swaminathan, J. Kim, I. Novak and J.P. Libous, “Power Distribution Networks for System-on-package: Status and Challenges,” IEEE Transactions on Advanced Packaging, Vol. 27, No. 2, May 2004, pp. 286-300.
  2. N. Na, J. Choi, S. Chum and M. Swaminathan, “Modelling and Transient Simulation of Planes in Electronic Package,” IEEE Transactions on Advanced Packaging, Vol. 23, No. 3, August 2000, pp. 340-352.
  3. J. Mao and M. Swaminathan, et al., “Modelling of Field Penetration Through Planes in Multilayered Packages,” IEEE Transactions on Advanced Packaging, Vol. 24, No. 3, August 2001, pp. 326-333.
  4. E. Engin and M. Swaminathan, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, Upper Saddle River, NJ, 2008.
  5. I. Novak and J. Miller, Frequency Domain Characterization of Power Distribution Networks, Artech House, Norwood, MA, 2007.
  6. X. Ye, D.M. Hockanson, M. Li, Y. Ren, W. Cui, J.L. Drewniak and R.E. DuBroff, “EMI Mitigation with Multilayer Power Bus Stacks and Via Stitching of Reference Plane,” IEEE Transactions on Electromagnetic Compatibility, Vol. 43, No. 4, November 2001, pp. 538-548.
  7. CST STUDIO SUITE 2012®, www.cst.com.
  8. A. Ciccomancini Scogna, “PPW Noise Mitigation in Multilayer PCBs by Means of Virtual Island and/or Array of Shorting Vias,” 2007 Proceedings of the Electromagnetic Compatibilty Conference.
  9. O.M. Ramahi and V. Granastein, “Novel Planar Electromagnetic Bandgap Structures for Mitigation of Switching Noise and EMI Reduction in High-Speed Circuits,” IEEE Transactions on Electromagnetic Compatibility, Vol. 49, No. 3, 2007, pp. 661-669.
  10. A. Ciccomancini Scogna, A. Orlandi and T.L. Wu, “Noise Coupling Mitigation in PWR/GND Plane Pair by Means of Photonic Crystal Fence: Sensitivity Analysis and Design Parameters Extraction,” IEEE Transactions on Advanced Packaging, to be published.

Antonio Ciccomancini Scogna received his doctorate in electrical engineering from the University of L’Aquila, Italy in 2005. He is Principal Engineer at Computer Simulation Technology (CST) of America, Framingham, Mass. His research interests include EMC numerical modeling, printed and integrated circuits, electromagnetic packaging effects, signal integrity and power integrity analysis in high speed digital systems.

Jianmin Zhang received his master’s degree and doctorate both in electrical engineering from the University of Missouri-Rolla in 2003 and 2007, respectively. He first joined Cisco Systems as a Senior Hardware Engineer after graduation in 2007 and as a technical leader in 2011 subsequently. He has been focusing on signal integrity and power integrity R&D for high-speed interconnects and involving in design and analysis of high-performance networking products at printed circuit board, package, and system levels. His research interests include signal integrity, power integrity, SerDes modeling, EMI/EMC, PCB material characterization and de-embedding techniques.

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