Tanner EDA asks: "Is It Time for an Analog Comeback?"
At DesignCon 2012 on Tuesday, January 31st, Tanner EDA, providers of software for the design, layout and verification of analog and mixed-signal integrated circuits (IC), participated in a panel session on analog and mixed-signal design moderated by Brian Bailey. The panel session, entitled “Is It Time for an Analog Comeback?,” looked at how shrinking process nodes and high speed digital design are changing the very nature of digital design.
At one time it seemed as if analog was almost a thing of the past with designs converting analog signals into digital as quickly as possible, leaving only small amounts of analog off-chip. Today that analog circuitry has come on-chip. Radios and high-speed communications are now fully integrated; power-saving schemes are adding new types of analog content; signal integrity and high-speed issues often require analog analysis; and these are demanding better tools and flows to handle the mixed-signal aspects of a design. In addition, there are some parts of a design that operate at speeds greater than digital is capable of. With better tools, will the percentage of the chip consumed by analog increase again? Will the shrinking geometries cause even greater difficulties for analog?
Jeff Miller, Product Manager at Tanner EDA, represented the company on the five-person panel that also included Warren Savage, CEO of IPextreme; Mladen Nizic, Engineering Director for Mixed-Signal Solutions, Cadence; Harold Joseph, Director for PSOC Analog Marketing, Cypress Semiconductor; and Navaraj Nandra, Senior Director of Designware Marketing & Mixed-Signal IP, Synopsys.