The Analog Office®

The Analog Office® design suite is a modern and complete design system that is specifically architected and optimized from the ground up for analog and radio-frequency integrated circuit (RFIC) designs. Analog Office software leverages AWR's unique unified data model to provide designers with a concurrent, interconnect-driven and RF-aware design methodology for RFIC and module design. The fundamental data models within the software are high-frequency aware, permitting accurate extraction and modeling of all design elements, including active and passive devices, as well as interconnect, at high-frequency.

Analog Office design suite is built on AWR's open high-frequency design platform, enabling easy integration of RFIC design technology from system to final tape-out that includes:

* Design capture
* Synthesis
* Simulation
* Optimization
* Layout
* Extraction
* Verification

Key Features
* APLAC® simulator: Fully integrated with the industry-leading APLAC simulator for time-domain and harmonic balance simulations
* Intelligent Net™ 2 (iNet2): Automatic, intelligent interconnect modeling for faster and more accurate design, simulation, extraction, and chip interconnect layout
* Silicon inductors/spirals: Optional tie-in to Helic's VeloceRF for simulation and extraction of inductor-to-inductor and inductor-to-line coupling
* Parasitic extraction: Streamlined integration to OEA International's NET-AN 3D net extraction technology for on-the-fly interconnect extraction of multiple silicon nets
* EM Socket™: Open EM Socket interface enables integration with the industry's best EM tools for effortless EM simulation of ultra high frequency interconnects
* Physical validation: Interface to industry tools such as Mentor's Calibre DRC/LVS and Cadence's Assura DRC
* Multiple technology support: Mixed designs/technology support enables seamless IC - package - module and board co-design
* Foundry support: Validated foundry RF process design kits (PDKs)
* Interoperability support: Support for the interoperable PCell libraries (IPL) and OpenAccess database from Ciranova and Cadence respectively


* Openness of flow: Delivers a complete, proven design flow, which can be enhanced through integration with best-in-class third party tools
* Reduce design cycle time: faster time-to-tapeout and time-to-market as unified data model accelerates RF closure
* Right the first time: Work correctly the first time given high-frequency accurate models and analysis of high performance analog/RF designs
* Quick learning curve: Intuitive design environment enables fast adoption and short ramp-up time
* Easy to install and maintain: Simple Windows installers used for Analog Office and PDKs enables you to install and run the sofware in minutes, not hours
* Compatibility: Advanced software architecture reduces tool & flow integration effort while AWR's open system philosophy provides seamless integration of best-in-class tool

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