New Physical Connectivity Engine for Native High Frequency Interconnect Verification
Microwave engineers have been forced to verify the validity of their high frequency design interconnects either by manual inspection or by using layout versus schematic tools designed for analog/digital design. Such tools, which are well established for low frequency design, tend to be less than optimal for high frequency microwave design, because they do not consider critical high frequency elements, such as how simple wires in schematic may become transmission lines in layout and may need special consideration.
This issue is addressed with a new layout connectivity engine in the Advanced Design System (ADS) 2004A release that can help microwave designers check the validity of their designs’ physical as well as nodal connectivity without overlooking important high frequency attributes. The new physical connectivity engine accomplishes this by extracting the physical and nodal connectivity information together during layout editing. This approach gives logical connectivity checks between schematic and layout a high frequency character. Together with new area/edge pins, physical interconnect hierarchical highlighting and improved layer binding definition, microwave designers now have a layout verification tool that saves time and reduces design uncertainty prior to prototyping.
Interconnect Extraction and Verification
The physical design interconnect verification step has often been overlooked in microwave design, mainly due to the simplicity of microwave IC or hybrid designs. As the commercial wireless markets began to expand in the 1990s, so did the complexity of monolithic microwave ICs (MMIC), while process dimensions began to shrink. Similarly, hybrid microwave designs increased in design complexity as microwave designers tried to pack more functionality into lighter (lower cost) modules.
With increases in microwave design complexity, the physical verification step of an MMIC design flow became more and more important. This step includes three key elements: electromagnetic (EM) verification of critical components in the design’s layout; design rule check (DRC) against manufacturing process rules; and physical design interconnect verification. The first two elements have established tools and methodologies. For the interconnect verification element, microwave designers were left with tools designed for analog/digital design that had an inherent separation between the logical (schematic) and physical (layout) domains. These tools were designed with the knowledge that schematics were built by designers, and layouts were generated by layout professionals. Therefore, design interconnect verification is performed in two steps:
(1) Extract one interconnect netlist from schematic and one from layout.
(2) Analyze the design’s interconnect by comparing the two extracted netlists.
This approach worked well for low frequency analog/digital designs. However, for MMIC design, where microwave engineers traversed the schematic and layout domains on a regular basis early in the design cycle, this approach was less than optimal. The microwave designer needed to check the design interconnects between schematic and layout by first extracting a netlist from the schematic then from the layout, and then performing the analysis by comparing the two. This multi-step process was not very attractive to microwave engineers.
For this reason, Agilent EEsof EDA has been working on delivering a more suitable approach to physical interconnect verification, while maintaining the close working environment between schematic and layout for microwave designs. This approach is based on a new physical connectivity engine that provides polygonal-based layout connectivity, extended pin modeling, and on-the-fly interconnect extraction and verification.
New ADS Physical Connectivity Engine
The physical connectivity engine in ADS 2004A provides a new way to handle physical interconnects in ADS EDA platform. The new capability allows ADS users to establish electrical interconnects based on polygonal-shaped layout artwork, and performs interconnect information extraction on the fly.
Polygonal-based Layout Connectivity
Polygonal-based layout connectivity introduces a new paradigm to microwave-based designs. It removes interconnect constraints placed on microwave designers in the form of wires and traces, and provides the ability to establish electrical connections with polygonal-based layout artwork. In other words, microwave designers can now do what they have been doing for a long time, with the addition of having their custom-tailored native interconnect configurations exhibiting electrical connectivity.
The benefits of this new functionality are numerous. The primary ones include allowing microwave designers to work in an EDA environment that gives them the flexibility to start a design either in schematic or layout, implement custom-tailored layout interconnects (beyond simple traces), perform on-the-fly layout interconnect information extraction and back-annotate custom-tailored interconnects to the schematic.
Other benefits include more robust design crosschecks between layout and schematic–open connections, nodal and components’ value mismatches, zero-width wires in layout, overlaid components, layout shapes touching but belonging to different nodes, polygon/component overlapping and non-pin-to-pin connections. Significant improvements to design connectivity validation include polygonal shapes touching or overlapping but belonging to different nodes or not making a pin-to-pin connection. Before the physical connectivity engine was implemented, such potential connectivity problems went unchecked, mainly due to the lack of arbitrary layout artwork connectivity information.
Also, because ordinary polygonal shapes now exhibit electrical connectivity characteristics resembling real-world conditions, vertical electrical connections are now possible without requiring pre-built via components. This means that microwave designers are no longer limited to the availability of pre-built via components in design kits (for MMIC designs) or component libraries (for PC board and module design) to establish vertical electrical connections. Designers can also define pinless vias either in via macros or by overlapping layout artwork on a multilayered stack. The new pinless vias allow simplified vertical connections and eliminate the need to place via components in schematics as well as layouts, as shown in Figure 1. The top interconnects show two metals on separate physical layers not connecting. The bottom traces make a connection by a polygonal shape placed on the predefined via layer.
Another enhancement to ADS layout connectivity is the expansion of pins beyond the point-pin concept to include edge and area pins. This new capability is most useful for design kit and component library developers, because it allows them to define unique edge and area pins to their layout components, however simple or complex they may be. Figure 2 illustrates how implemented edge and area pins facilitate a more robust interconnect definition within ADS layout.
Physical/Logical Interconnect Verification
With the availability of a new physical connectivity engine in ADS, designers have an enhanced ability to perform robust interconnect verification. Because all polygonal shapes in layout carry electrical connectivity information, ADS users can perform a significant number of verification checks, including nodal and physical connectivity checks, at any point in the design process.
When it comes to back-end interconnect verification, the new engine provides capabilities not previously possible. The verification types are grouped into two areas — nodal interconnect check and physical interconnect check.
Nodal interconnect check lets ADS users check the design’s nodes in schematic and layout (the definition of node is understood as a pin/port and all touching interconnects, excluding design components, whether they are active or passive). This feature is very useful for performing schematic/layout nodal “cross-probing,” which allows microwave designers to verify the accuracy of their designs as simple wires in schematic transform into elaborate physical interconnects, as shown in Figure 3.
Physical interconnect check provides ADS designers with the ability to highlight all shorted (touching) metal in multilayer hierarchical designs. This feature allows for an easy-to-perform interconnect integrity check for a design’s physical layout. With a mouse click, ADS designers can easily tell what a given metal trace, path, polygon, or transmission line touches. Figure 4 illustrates how this feature works. Designers can now click on any metal in a given design and instantly see all other metal that shorts to it. This level of performance and ease of use takes physical interconnect verification to a new level.