- Buyers Guide
RFMD's IPC technology is complementary to its GaN technology, and other power semiconductor technologies, for the design of multi-chip modules (MCMs). With RFMD's IPC technology, foundry services customers can design integrated matching networks and other passive functions on RFMD's industry leading, low-cost gallium arsenide (GaAs) process technology, rather than place them adjacent to amplifiers and other active components. This allows RFMD's foundry services customers to reduce costs and achieve higher levels of integration by leveraging RFMD's industry-leading scale and cost structure in GaAs and GaN manufacturing.
RFMD's IPC technology provides all of the passive circuit components necessary to enable matching networks, including MIM capacitors, multi-layer stacked capacitors, thin-film resistors and inductors. Additionally, three metal interconnect layers are available for complex routing and increased current-handling capability.
Bob Van Buskirk, president of RFMD's Multi-Market Products Group (MPG), said, "RFMD's leading compound semiconductor scale, built to serve the cellular handset market, allows us to deliver industry-leading cycle time, yields and costs. We enable our foundry customers to take advantage of a compound semiconductor factory capable of shipping over two million RF components per day to bring speed, predictability and price advantages difficult to match."
RFMD's GaN Foundry Services business unit currently offers foundry customers access to two of RFMD's GaN process technologies: GaN1, targeted at high power, and GaN2, targeted at high linearity applications. RFMD's Foundry Services business unit was formed to supply RFMD's high-reliability, high-performance and price-competitive GaN processes and associated technologies to external foundry customers immediately upon process qualification and production release.
RFMD's Foundry Services business unit offers a secure website to customers for use as a collaboration tool for their work with RFMD's GaN foundry. All necessary tools and documents are current and readily available, including:
-- Monthly schedule for multi-project wafer shuttle runs
-- Process design kits (ADS, AWR) -- Design rule check and layout versus schematic runsets for layout verification using Calibre
-- Complete descriptions of the design rules
-- Step-by-step instructions for each stage of the foundry process
-- A private access folder for secured uploading and downloading of confidential files