This webcast describes how signal integrity issues with FPGAs, used in high-speed designs, can be minimized by properly modeling the signal path. The presentation will show how to model real world circuit boards using S-parameters, showing that it is possible to predict eye opening performance before a system is physically prototyped. A 90nm transceiver model is incorporated in Agilent’s Advanced Design System (ADS) as a library element, permitting system-level modeling of interconnects and FPGA transceivers. Both measured and modeled results and their correlation will be discussed, concluding that the new method is both execution time efficient and is sufficiently accurate to provide a high level of confidence for designers wishing to design serial links to 6.375 Gb/s. The presenters are Sanjeev Gupta, Signal Integrity Applications Expert, Agilent Technologies EEsof EDA Division, and Salman Jiva, Technical Marketing Engineer, Altera.