SANTA CLARA, Calif.--(BUSINESS WIRE)--Agilent Technologies Inc. (NYSE: A) today announced it will showcase its latest signal integrity design and RFIC verification innovations at the 2008 Design Automation Conference in Anaheim, Calif., June 8-13, Booth 1601. The products that will be demonstrated are geared toward analyzing and verifying today’s increasingly complex high-speed interconnect and RFIC designs. The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems as well as electronic design automation (EDA) and silicon solutions. As a leading supplier of EDA software for high-frequency system, circuit and modeling applications, Agilent’s EEsof EDA division will showcase its most recent innovations to the following design flows: Signal integrity; RFIC; MMIC; RF board/module; and Electronic Systems Level (ESL). Agilent EEsof EDA offers a wide array of RF and mixed-signal design solutions that include the Advanced Design System RF EDA software, with solutions for signal integrity design and electromagnetic simulation and analysis; GoldenGate for large-scale RF/mixed-signal IC simulation and design-for-yield in the Cadence design environment; and SystemVue for RFIC system architecture. In addition to technical meetings and presentations at the conference, Todd Cutler, senior director with Agilent’s EEsof EDA division, will serve on a panel session titled “Electronics and Politics: What the Industry Needs from the Incoming U.S. Administration.” Panelists will discuss the U.S. presidential candidates’ proposed initiatives and changes that potentially affect the DAC community. For more information about Agilent’s participation and schedule at DAC 2008, visit www.agilent.com/find/eesof-dac2008. For general information about the conference, visit http://www.dac.com/45th/index.aspx. For information about all of Agilent’s EEsof EDA products and solutions, visit www.agilent.com/find/eesof.