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In the Agilent/MWJ Innovations in EDA webcast on “Discrete Oscillator Design Tools and Techniques”, Randy Rhea presented a discrete oscillator design using the Genesys product from Agilent, using techniques outlined in his new book “Discrete Oscillator Design: linear, nonlinear, transient and noise domains”. The method outlined by Rhea begins with a linear analysis as a first step.
Its tempting to being with a nonlinear closed loop simulation with oscillation, but in doing so you are no more informed than with a circuit oscillating on the bench. What’s the gain margin? Does the maximally loaded Q occur at the oscillation frequency? What if it doesn’t oscillate at all?
Linear analysis provides that foundation. It identifies the design margins, it’s a fast and simple way to study the tuning characteristics, and it can be used for initial estimates of phase noise. It is also quick for exploring new topologies and basic design ideas. More importantly, a linear analysis provides valuable insight into the design process, though it’s a simplified view it provides an intuitive understanding of how oscillators work.
Unfortunately, it only provides a qualitative grasp of the operating power levels, harmonic output or transient behavior. That information can be obtained with subsequent harmonic balance analyses.
Two methods are used for linear analysis. A popular method for microwave oscillators particularly for VCO designs is the one-port reflection method. Most authors refer to this technique as the “negative resistance analysis”. Actually, they’re both negative resistance and negative conductance oscillators. The difference is not merely a matter of semantics. The negative resistance oscillator must use a series resonator and the negative conductance oscillator must use a parallel resonator. The initial analysis of the negative resistance oscillator is performed by looking into the device through a series resonator. To form the oscillator, the test port is removed and that port is grounded. The initial analysis of the negative conductance oscillator is performed by looking into the device across the top of a parallel resonator. To form the oscillator, the test port is removed and that port is left open. In some circuits, the oscillator does not include a node where the loop can be opened. In this case, the negative resistance or conductance analysis method must be used.
The other approach, the open loop method has been preferred for years at lower frequencies, including crystal oscillators. I prefer this method, even for microwave oscillators. It provides more insight into numerous oscillator behaviors. It also allows estimation of the loaded Q, this is a very important measure of oscillator performance. The open-loop cascade technique also avoids some of the confusion that comes with using the one-port reflection or negative resistance/conductance techniques. For this reason, I use the open-loop cascade method to consider a 40MHz Colpitts oscillator with a FET and an L-C resonator, this is a typical of common drain (or common collector) oscillators, where the source (or emitter) is connected to the capacitive tap. For the open-loop method, the circuit is opened between the source and the capacitive tap. The open –loop input port is at the capacitive tap (loopout) and the cascade output port is at the source (loopin). The capacitor c3, shown in the circuit schematic shown below, is used to couple output power from the oscillator into a 50 ohm load. Capacitor c4 is used to avoid the simulator’s termination resistance from disturbing the oscillator bias. With a common drain amplifier, the output impedance at the source is generally low and the input impedance at the gate is high. The capacitive tap transforms the low impedance of the source up to the high impedance at the gate. In this example, I use an initial loop termination resistance of 50 ohms. One can also “open” the loop at the gate, the impedance at this node is higher and so a higher port resistance would need to be chosen.
So what are the oscillator starting conditions. Oscillation occurs at the phase zero-crossing if the initial linear gain margin is greater than 0 dB. Oscillation does not occur at the gain peak, it occurs at the phase zero-crossing and the phase slope should also be negative at the zero-crossing. The phase characteristics are more important than the amplitude characteristics. When a change occurs in the transmission phase due to temperature, load or other event, the oscillation frequency will shift up or down. With shallow slope, the frequency shift is large. With steep slope, the shift is smaller. Therefore, the phase slope should be as steep as possible. To take advantage of the phase slope, its desirable if the phase zero crossing occurs at the maximum phase slope.
Too low of a gain margin increases the risk that gain changes might prevent oscillations and also results in slow starting. Too high a gain margin leads to heavy compression and a worsening of the phase noise and potentially oscillator instabilities. 3 to 8 dB is a reasonable gain margin for most oscillators. The amplifier should be stable, it’s the positive feedback from closing the loop that causes oscillation. Amplifier instability can result in spurious modes. To utilize the available device gain, the maximum response gain should occur at our near the phase zero-crossing. This is the least critical characteristic and tends to occur naturally when other objectives are satisfied.
The predicted response of the open cascade assumes the cascade is terminated by the simulator, later when the loop is closed, the terminations are provided by the circuit itself. For the analysis to be accurate, the loop matching should be good. The plots below show the transmission and reflection responses of the 40 MHz Colpitts circuit using the open-loop cascade. The transmission plot on the left shows the gain (in red), which peaks at about 3 dB, the low end of our target. Also shown on this plot is the transmission phase (in blue) or the angle of s21 and the loaded Q (in green). Clearly, the phase crosses zero at the desired 40 MHz. The was previously adjusted the capacitors c1 in the oscillator to ensure that the phase zero crossing would occur at the target frequency of 40 MHz. The loaded Q is computed by the simulator from the transmission phase slope; the higher the loaded Q, the steeper the phase slope. In this case the loaded Q is about 10.
The reflection data is plotted as s11 and s22 on the Smith chart. The s22 is reasonable at around 12.7 dB return loss, however s11, the input match at 40 MHz is only about -0.34dB. The mismatch is so poor that the simulated transmission characteristics plotted on the left are significantly are more or less useless. Historically, this problem was managed by redesigning the cascade for better open loop input and output match. Matching network are not added because this increases circuit complexity and potentially adds additional resonances. Rather, the matches are improved by adjusting the capacitors in the tap. Changing the simulator termination impedance to some other value can also be used to improve the simulation match. But maintaining the termination at 50 ohms makes it easier to confirm the prototype using a standard network analyzer.
To improve the open-loop response, the simulator’s (Genesys) optimizer was used to modify component values so that the overall circuit goals were achieved. These goals included improving both the input (s11) and output (s22) match to better than -12 dB, a loaded Q of greater than 30, a gain (s21) equal to 6 dB and a phase zero crossing at 40 MHz. Each goal was given equal weighting. The results of an optimization, which took about 20 seconds, are shown below. Optimized component values were replaced with the nearest standard component values and the circuit was re-tuned manually to shift the frequency back to 40 MHz.
This is a quick look at using the open-loop response method with the Genesys circuit simulator from Agilent EEsof EDA. The lengthier description of this design, including non-linear analysis were presented in a special webcast hosted by Agilent Technologies and Microwave Journal on September 16th, and is available for viewing . More information on Oscillator design is available in my book, s, available from Artech House.
This is a list of questions posed after my Agilent webinar presentation: Oscillator Design with Genesys. I must say, responding to these questions brought back many memories for me, and it was a lot of fun”, Randy Rhea 16 Sept 2010
ANSWERS: I will answer these five match questions as a group. The issue of match in the open loop cascade has always generated a lot of questions, and skepticism, in my oscillator classes. I’ll try to explain it in steps.
Point 1: While the idea of an amplifier matched to 50 ohms is easy to accept, it may be difficult to accept that a resonator consisting of only reactors can have a resistive input impedance. Consider a simple series resonator cascaded with a 50 ohm amplifier. At resonance, the reactance of the series inductor and series capacitor cancel, and the impedance seen looking into the resonator is the 50 ohms of the amplifier. The cascade input is matched to 50 ohms! So to obtain a matched open loop it is only necessary to have a matched amplifier.
Point 2: Consider slide 10 of the presentation. This is a simple, but typical, FET Colpitts oscillator. Even though a FETs input impedance is high, notice that after optimization, the cascade input return loss is 12.7 dB. The Colpitts resonator matched 50 ohms to the gate. In this case, the source impedance is naturally well matched to 50 ohms with a 17.8 dB return loss.
Point 3: Why 50 ohms? First of all, don’t become hung up on this idea. From the simulator’s standpoint, you can chose any equal and resistive termination impedance: 1 ohm, 50 ohms, 1Mohm. You simply choose the resistance that best matches the source and then use the capacitive tap to match the gate to that resistance. It is often 100 to 200 ohms for a low-frequency FET. As you go up in frequency, it tends lower in impedance. The same process is used regardless of the device, or type of resonator, ei, whether it is a Pierce, Colpitts, Clapp or whatever. You’ll be surprised how often the selected impedance can be close to 50 ohms, and that is convenient for confirmation on the bench. 50 ohms is merely convenient, not required.
Point 4: Don’t worry about matching to 20 dB return loss. It is wasted effort. In an oscillator, there is no advantage to knowing the gain margin to fractions of a dB. The simulation will be reasonably accurate with 12 dB return losses. For the simple, uncorrected S-parameters to be an accurate simulation, with a reasonably small S12, only EITHER S11 or S22 needs to be small. To understand this statement, test it against the Randall/Hoch equation.
Point 5: If you are having trouble getting a reasonable match, at any chosen reference impedance, be sure to assess stability. CB, CC, CG and CD amplifiers, typically used with Colpitts oscillators, are notoriously unstable. That is why these configurations are used in negative resistance and negative conductance oscillators. A sure sign of instability is either or both of the loop port impedances plotting outside the circumference of the Smith chart somewhere in the frequency range. If this is the case, before beginning the analysis, stabilize the device with resistance in series with the base or the emitter. Be sure to assess how this degrades the noise figure. This resistance not only makes the simulation go better, it reduces potential spurious modes in the oscillator.
Point 6: This point addresses the questions of the simulator loading the resonator. Consider again slide 10 in the presentation. After optimization, both ports are well matched. That means the source is near 50 ohms. The simulator termination was set to 50 ohms. Therefore, when the loop is closed, the source will terminate the tap with the same impedance that the simulator did!
Final Point: If the cascade does not optimize to a reasonable match, or if the gain margin is small and you need a more accurate simulation, or if you are just skeptical, then use the Randall/Hoch correction. Their G is the true open-loop gain with the cascade self-terminating. G is exact. You may measure the initial loop S-parameters with ANY reference impedance, and you may even open the loop at ANY node, and the result for G is identical, including the phase slope of G, which defines the loaded Q. Computing and displaying G in Genesys is a snap.
ANSWER: The attendee is remarking about the fact that the frequency range set in the optimization goals displayed in slide 9 was 39.9 to 40.1 MHz rather than 40 MHz. This is simply an old habit of mine, because digital computers use floating-point math when computing frequency points in a sweep. If the step point for 40 MHz computed as 39.99999999999999 there would be no data point at 40 MHz. For 15 years, I haven’t tested if this old habit to see if its still necessary.
ANSWER: The loaded Q computed by Genesys is derived from the slope of the forward transmission phase. Loaded Q is also defined as the center frequency divided by the 3 dB down amplitude bandwidth of a single resonator. However, with oscillators, we are primarily concerned with the phase. Also, the phase definition is somewhat more consistent with multiple resonators.
Well yes, the objective is to keep the phase zero crossing at the desired frequency under all conditions. In fact, if we were perfectly successful in doing so, there would be absolutely no long term (drift) or short term (noise) frequency deviation.
In practice, the absolute value of the transmission phase can change with temperature, noise, supply and load changes. Examine the response of the transmission phase. Now imagine the entire curve shifts up or down in phase. If the slope is shallow, a large shift occurs in the zero crossing frequency. Now image the slope is infinitely steep. In that case, the frequency shift resulting from a phase shift is zero! Wouldn’t that be nice?! That is why a steep phase slope (which is high loaded Q) is so important.
ANSWER: Yes. In English it is spelled Cayenne. It is a hot spice named after the city in French Guiana. This is obviously a name play on the popular simulator family SPICE, originally from UC Berkeley. Cayenne is not a derivative of SPICE, but like SPICE, it is a time-step simulator. Cayenne uses the same nonlinear models that both the Genesys linear and HARBEC harmonic balance simulators use. Genesys can import SPICE models.
ANSWER: That is a great question because it points out a strength of time-step simulation. With a real oscillator, when not powered, all voltages rest at zero. When power is applied, the rising supply voltage begins to charge the bias and resonator circuitry. A time-step simulator emulates this process with small time-step changes propagating through the circuit. If you draw your schematic and apply a power supply turn-on step, Cayenne accurately simulates the actual starting process. No “artificial” starting techniques are needed. You also have the option in Cayenne to begin at time zero at the quiescent, steady state bias conditions. You do not use this option when simulating starting.
ANSWER: The short answer is up to any frequency where the components are described with electrical models. In practice, the answer to this question is very complex. The difficulty is with the models. Genesys includes all well published models for lumped and distributed passive components, and these same models are used in all commercial simulators on the market. The answer also depends on the details. For example, the basic model for an inductor with a 1 cm diameter may fail at 100 MHz, while the same model for a 0.1 mm diameter inductor may work well through 10 GHz. To successfully use any simulator, and Genesys is no different, the engineer must be willing to study components (and a simulator helps here also) before building a circuit. Nevertheless, up to about 500 MHz, except for some filters, standard simulation techniques should suffice.
Above 500 MHz, the successful engineer will spend as much time characterizing components as he does simulating his circuits. Above about 2 GHz (again depending on the specific circuit), electromagnetic simulation (EM) should be added to the toolbox. Another factor influencing whether EM simulation is required is the distributed process used. For example, there are well-engineered circuit-theory models for numerous microstrip objects. On the other hand, the models available for coplanar objects are more limited. There may be no models for less common, special layer configurations. In this case, EM simulation is mandatory.
ANSWER: State of the art in oscillator design often involves phase noise. Scores of manufacturers of crystal and microwave oscillators have years of in-the-trenches experience in achieving the ultimate in phase noise. It is hard to describe how minute a perturbation can cause noise at –170 dB or more below the carrier. In my first year as an engineer, I battled phase noise in a magnetron for days until I discovered it was the fan-bearing noise of a spectrum analyzer on the bench vibrating the magnetron. Ten years later, I battled a phase noise issue until I discovered that a florescent light was modulating an IC through its black plastic package. I have only a few paragraphs, but I’ll describe some key points. The book devotes Chapter 4 to the topic, and even then, it certainly isn’t comprehensive.
Yes, the most important parameter is the loaded Q, because phase noise improves with the square of loaded Q. It is important to recognize the difference between loaded and unloaded Q. Unless the loaded Q is very high, improving the component (unloaded Q) will have little effect on performance.
Next in importance is the oscillator power level. Since the noise is a fixed level, increasing the carrier level improves noise in relation to the carrier, in dBc. Higher power resulting in lower noise might seem counterintuitive, and it often generates as much skepticism as the open loop cascade match issue. However, increasing oscillator output power improves phase noise, almost linearly, and there are several measured data examples in the book. In most active devices, increasing the current and power level degrades the noise figure to a degree, but not nearly as rapidly as it improves the phase noise. Unfortunately, increased output power requires increased device current, which is often not acceptable for battery-powered applications. Amplifying the signal after the intrinsic oscillation process is of no benefit because it amplifies both the noise and the carrier. Also, operation above a few milliwatts may crack a quartz crystal, so higher power in not an option in crystal oscillators.
Third in importance is device selection. While improving the noise figure makes common sense, today the difference in the noise figure of a state of the art device and an inexpensive one is 1 or 2 dB. One thing that is important about device selection is flicker noise. Bipolar and FET devices typically have low flicker noise and it doesn’t matter which is chosen. However, GaAs devices have horrible flicker noise below 1 MHz. While this is not an issue in high frequency amplifiers, it is terrible for oscillators, because this low frequency noise becomes upconverted around the carrier.
Yes, to both parts of the final question: it is a good idea to worry about the impedance presented to the amplifier with regard to the effect on noise figure, and the noise figure of an amplifier predicted by Genesys is available for use Leeson’s equation. However, keep in mind, a 1 or 2 dB improvement in noise figure may be minor in relation to focusing the design on higher loaded Q and power level.
ANSWER: For a single pole resonator, the loaded Q, group delay and 3 dB amplitude bandwidth are related by simple equations given in the book. Higher loaded Q is achieved with narrower bandwidth, which is achieved by more extreme reactor values, or better, by resonator coupling. For a given unloaded Q, increasing the loaded Q unfortunately increases the resonator insertion loss. This is what limits loaded Q (resonator voltage overdriving a varactor may also limit the loaded Q). Too much loaded Q and the active device can’t overcome the resonator loss.
It is true, that given a maximum acceptable loss, say 10 dB, that multiple resonators can achieve a steeper phase slope for a given component (unloaded) Q. Two resonators don’t double the loaded Q for a given loss, its more like a factor of 1.4. With three resonators, its around 1.5. This is easily explored using a linear simulator. This should improve oscillator phase noise performance. Whether it does, and what the “shape” of the phase noise curve is with respect to offset frequency, needs further investigation. I would be interested to hear about what you learn regarding this.
When the supply voltage changes, the bias and phase shift of the amplifier will change. If the supply voltage change is noise, then noise is modulated into the oscillator. This is easily quantifiable and predictable and equations are given in the book. Higher loaded Q reduces this problem as well.
Therefore, it is important to have a well-regulated supply to the oscillator. You can test if supply noise is an issue by temporarily replacing the supply with a battery. Chemical batteries have extremely low noise voltage.
The noise properties of IC voltage regulators vary widely. Once, while observing oscillator phase noise during a spectrum analyzer sweep, I noticed that the phase noise erratically stepped up or down by 10 dB, over a period of a few minutes. A can of spray coolant quickly isolated the problem to a small, plastic voltage regulator. Since then, I tend to use simple RC filtering for low power oscillators that don’t draw much current, or discrete voltage regulators in higher power oscillators. If I were to use an IC voltage regulator, I would at least use a high quality regulator with controlled and specified noise performance.
Feel free to post questions and comments here.
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