EM Analysis within the Design Flow

Modern RF/and microwave design flows make extensive use of electromagnetic (EM) analysis in many ways, and its co-existence and concurrency with circuit design and analysis can not be underestimated. Prior to the circuit design and especially in larger designs, EM tools are used to create “library” parts such as inductors, transitions, and antennas. While these parts are fairly self-contained, they must ultimately be integrated into the overall design where at the very least they must be connected to the rest of the circuit or in a more complex case be coupled to it. During both early and later stages of design, designers will switch from circuit-based models to EM analysis of critical interconnects to better understand couplings and achieve greater accuracy. EM analysis is used again before the design goes to manufacturing, so that the metal in the design can be analyzed one more time to verify circuit performance alongside design rule check (DRC), layout versus schematic (LVS), and even design for manufacturability.

An overriding issue common to all these applications is that at some level the EM solver must interact with other tools. The raw materials that the solver takes as input are geometries or structures, but are no more than a layout with electrical material properties for all the layers. At the other end of the process, the EM solver produces S-parameters or some other linear model representation. Some solvers can output SPICE netlists directly, which must be integrated with the rest of the design in a circuit simulator. Achieving all this successfully has historically been a less-than-seamless chore of duplicating geometries or exporting and importing structures from the design or layout tool to the solver. The results must then be imported into the circuit simulator. While much effort has gone into automation of moving GDSII or DXF from layout tools to the solver, most of these tools lack real-time integration and have a “batch mode” feel, as though things were “auto-magically” going on behind the scenes. There has also been little to help integrate the results back into the schematic, especially when using the solver in a verifi cation mode. Dozens if not hundreds of ports are involved in fi nal verifi cation, and it is often left to the designer to put together a schematic that properly reattaches each port in the solver’s results to the proper pins of the remaining components. This must be performed without error, and quickly, in order to get the design out the door.

This design flow conundrum is one that AWR works hard to mitigate. The problem of EM concurrency and co-design within an overall circuit fl ow was voiced by AWR’s customers, and in response, the company’s R&D team created the AWR EXTRACT™ fl ow, that is, schematic-driven EM analysis. With an EXTRACT element on the schematic, the design is ready to automatically create EM documents from the schematic’s layout and then seamlessly reintegrate the results back into the schematic as part of any circuit simulation, optimization, and/or tuning step. EXTRACT is easy to use and incorporates some very complex, innovative technology to solve a host of design issues related to the inclusion of EM analysis into the overall design fl ow process.

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