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Industry News

Remtec Has Developed Innovative Flip Chip Packaging

November 18, 2011
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Remtec, a leader in ceramic packages based on Plated Copper on Thick Film (PCTF) technology, has developed an efficient, cost effective chip scale packaging approach for flip chip power devices. It allows for simple, effective packaging of various Si, SiC and GaN FET transistors -- MOSFETs and eGAN transistors amongst others -- in the form of interposers and hermetic packages for single devices or multi-chip modules (MCM), often integrated with discrete components in a significantly smaller footprint, reaching system-in-package (SIP) level.

Using its PCTF technology, Remtec is able to maintain low DC resistance thick copper tracks and copper plated vias in ceramics (less than 1 mΩ) that ensure minimal DC losses and inductance; it allows higher than 20 amp current capability and faster switching times. For example, the switching speeds of power MOSFETs are reduced from 3 ns to 1 ns. Equally important to designers seeking miniaturization is the 4 to 6 time reduction in footprint size.

Remtec’s packaging technology offers designers interposers and packages with lower development costs, more rapid time-to-market, user-friendly flip chip assembly capable meeting BGA footprint, with effective heat dissipation and high reliability. The ability to integrate gold tin layers in the package base makes final assembly significantly less expensive. Using these features, designers can now meet the ever-increasing need for lower cost, higher power density and increased integration levels.

Remtec’s innovative packaging technique is used in high speed power MOSFETs for drivers, DC/DC converters, RF transmissions, network and server power supplies and other power electronic applications.

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