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Altis Semiconductor, a leading innovative European specialty foundry, is collaborating with Cadence® Services to migrate and enhance various versions of its 130 nanometer process design kits (PDK) supporting the latest release of Cadence Virtuoso® custom IC design technology.
Cadence Services provided a migration script to ease the migration of existing legacy designs to the new PDK structure. The structure of the design-ready PDK is optimal for Altis customers using Virtuoso v6.1 and the OpenAccess database. The PDK is now set up for easy maintenance of the different process variants such as low power, RF, or flash, as well as for the different metal stacks using the Incremental Tech Data Base (ITDB) and single source concept.
"Altis' strength is the ability to develop customers' dedicated technology derivatives for RF CMOS applications, embedded memories IPs, silicon photonics, or innovative microsystems products,” said Gianmaria Mazzucchelli, Vice President, Design Center, Altis Semiconductor. "Using leading analog/custom and mixed-signal technologies from Cadence, we are ideally positioned to efficiently generate PDKs, fulfilling our customers’ needs in terms of dedicated features, specific devices and design tools implementation, improved productivity and quality excellence.”
Altis customers will receive a PDK containing a rich set of SKILL parameterized cell generators and the support of advanced interactive and automation technologies such as design-rule-driven editing and the Virtuoso Space-based Router for custom chip, block and device-level routing. To enable its customers to achieve first-time silicon success, Altis deploys Cadence QRC Extraction for parasitic extraction.
“PDK development requires special skills and methodologies. The high quality of a PDK makes all the difference in creating a truly differentiated product. We worked closely with Altis to ensure that all their specific requirements were matched and delivered in a timely manner. The PDKs match Altis’ technologies and allow the highest quality designs, supporting first-pass silicon success,” said Peter Groos, services director EMEA at Cadence.
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