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Tackling the Mixed-signal Testing Challenges of SDR
Software-defined radios (SDR) utilize a combination of FPGAs, DSPs and analog/RF designs to achieve the radio’s system performance. The mixed-signal nature of these SDR designs can introduce system integration testing complexities when the baseband hardware and RF hardware are integrated and tested together. This testing complexity presents itself because the SDR’s overall system performance can be impacted by an accumulation of baseband, analog and RF design impairments, which can make issues difficult to isolate in the system integration testing phase.
An example is an FPGA finite impulse response (FIR) filter implementation, impacting the waveform quality and contributing to the SDR’s overall measured error vector magnitude (EVM) performance. Additionally, the D/A converter may introduce nonlinearities and the D/A converter clock may introduce jitter, which can also impact the SDR’s EVM performance. LO phase noise, IF/RF filters and nonlinear gain/phase distortion from the IF/RF up-converter and power amplifier can also introduce waveform distortion to the SDR’s EVM performance. Thus, the SDR’s overall EVM performance is an accumulation of each of the error contributions along the mixed-signal transmitter chain.
SDR orthogonal frequency division multiple access (OFDMA) technologies can also employ multiple-input multiple-output (MIMO) technologies to increase data rates relative to single-input single-output (SISO) approaches.1 MIMO spatial multiplexing algorithms, multiple transmit/receive IF/RF chains, and multiple antennas and impairments, such as timing errors and cross-coupling between the multiple channels,2 can further contribute to these mixed-signal testing and debugging complexities.
These problems highlight the need for an improved methodology to probe at various stages along a mixed-signal chain. This enables system engineers to gain insight into the incremental impairments introduced to the waveform at every stage of the mixed-signal SDR design. Furthermore, probing at various stages of an FPGA implementation and debugging with the same vector signal analysis (VSA) measurement software used to measure the analog IQ, IF and RF stages can provide an additional level of insight into issues occurring in the FPGA implementation itself. This article reveals several case studies, which highlight an improved test methodology for mixed-signal SDRs.
An Improved SDR Mixed-Signal Testing Methodology
The improved SDR mixed-signal testing methodology shown in Figure 1 illustrates how the SDR system engineer can probe at various stages along a mixed-signal chain. This methodology enables the engineer to gain visibility into the incremental impairments occurring along the mixed-signal transmitter chain, and can also be used in debugging issues in the system integration testing phase. Vector signal analysis (VSA) software is used on both a logic analyzer and a digital oscilloscope to analyze the waveform distortion and EVM at various stages along the SDR mixed-signal chain.
An FPGA dynamic probe can be used with the logic analyzer to select intermediate digital probe points (signal banks) within an FPGA implementation. The probe points can be demodulated with the VSA software to determine the effects of the FPGA’s implementation on the SDR’s EVM error budget (that is measuring the EVM performance of a FIR root raised cosine filter). When probing along a MIMO physical layer coding chain, the dynamic probe capability can also be used to compare the measured test vectors with expected vectors to find issues such as bit reversals.
Once the SDR waveform has been converted to analog with D/A converter(s), it can be measured at various stages such as analog IQ, IF, or RF using a digital oscilloscope with the VSA software. This allows the engineer to determine how various analog impairments such as LO phase noise, IF/RF filters, and nonlinear gain/phase distortion from the IF/RF up-converter and power amplifier (PA) are impacting the SDR’s EVM performance.
The VSA software provides measurement continuity between the digital domain using the logic analyzer and the IQ, IF, RF domain using the digital oscilloscope. This enables the engineer to diagnose issues and gain insight into waveform impairments in both the digital and analog/RF domains. Many commercial-off-the-shelf (COTS) signal formats are supported by VSA software, including OFDM and OFDMA signal formats. Two- and four-channel MIMO demodulation can be performed using a digital oscilloscope with the VSA software for OFDMA waveforms such as LTE.
Several case studies will now be examined, including a mobile WiMAX™ case study, using the logic analyzer and the FPGA dynamic probe with the VSA software. An LTE MIMO case study using the digital oscilloscope with the VSA software will also be examined.
Figure 2 Mixed-signal SDR test setup using a logic analyzer with dynamic probe and VSA software and a digital oscilloscope with VSA software.
Mobile WiMAX Case Study
The test setup shown in Figure 2 is used to probe at various stages along a Mobile WiMAX IQ modulator FPGA implementation using a logic analyzer with FPGA dynamic probe (left). An FPGA dynamic probe is used to select various internal FPGA signal banks, which are then demodulated by the VSA software in the logic analyzer (left) to evaluate the FPGA design at various probe points in the implementation. The FPGA development board being tested also has a D/A converter to convert the digital IF to an analog IF, which is then demodulated by the digital oscilloscope (right) and the VSA software in the oscilloscope.
Figure 3 FPGA dynamic probe banks for mobile WiMAX IQ modulator implementation.
Figure 3 graphically illustrates the FPGA implementation being probed and shows the signal bank selection menu in the logic analyzer. IQ data at 1 sample/symbol are stored in LUTs, then up-sampled with 4× oversampling and FIR filtered. The up-sampled and filtered IQ are then digitally modulated on a digital IF carrier using an Fs/4 multiplexing technique. A signal bank has been created for each of these points along the signal path.
Xilinx Chipscope Pro is used to configure the debug MUX ATC2 core. The core allows the user to quickly access incremental sets of internal signals in a mouse click. For this example, the core has been configured with four banks of pre-selected signals, three of which are highlighted here. They include: 1) FIR inputs at 1× oversampling; 2) FIR outputs with 4× oversampling; and 3) multiplexed digital Fs/4 IF output (DAC inputs) with 4× oversampling.
Through the logic analyzer interface, a test point can be selected, which switches the MUX inside the FPGA to bring out the particular signal of interest. That signal, such as the FIR filter output, is captured in the logic analyzer memory and is then exported to the VSA software. The signal is demodulated and analyzed with the VSA software.
Figure 4 FPGA dynamic probe measurement result showing demodulation at various stages of the IQ modulator implementation.
Figure 4 shows the demodulation results at each of the three test points: FIR inputs at 1× oversampling (left), FIR outputs with 4× oversampling (middle) and multiplexed digital Fs/4 IF output (DAC inputs with 4× oversampling (right)).
Figure 5 D/A converter board output measured with the digital oscilloscope and VSA software.
The VSA demodulation and spectrum measurements in the figure show the performance at various stages along the FPGA implementation. The spectrum on the left VSA display shows the aliasing in the unfiltered waveform with 1 sample/symbol. The EVM is approximately 0.3 percent RMS. The spectrum on the middle VSA display shows the 4× up-sampled and FIR filtered waveform. The EVM is slightly degraded at approximately 0.6 percent RMS, due to the FIR tap coefficients implemented in the FPGA. The spectrum on the right VSA display is the digital IF spectrum centered at 11.2 MHz, which is Fs/4 for the 44.8 MHz clock being used for the D/A converter. The EVM is again incrementally degraded (relative to the FIR outputs) at approximately 1.2 percent, due to the distortion introduced by the Fs/4 fixed-point multiplexing used to generate the modulated digital IF. This particular implementation does not reveal any significant issues; however, this methodology would provide insight issues if they were occurring (such as incorrect tap coefficient in one of the FIRs). The demodulation results at the D/A converter output and measured with the digital oscilloscope are shown in Figure 5.
The D/A converter output EVM (measured with the oscilloscope) is approximately 1.3 percent, and is not significantly different than the EVM measured at the D/A converter digital inputs with the logic analyzer. Thus, the D/A converter is not contributing significant waveform distortion in this example. However, this shows an approach to measuring the waveform EVM distortion contributed by an SDR’s D/A converter.
Figure 6 FPGA two-channel MIMO test setup with digital oscilloscope.
LTE Case Study Using Digital Oscilloscope for MIMO Demodulation
The FPGA board used in the previous case study is re-configured with a bit file for two-channel LTE MIMO. The development board has two D/A converters, enabling it to be used for two-channel MIMO. Multi-channel oscilloscopes, with the VSA software, are well-suited for two- or four-channel MIMO applications, due to their multi-channel phase coherent inputs. A two-channel MIMO test setup with a digital oscilloscope is shown in Figure 6. MIMO demodulation requires well-conditioned timing between the antenna channels to maintain orthogonality of the reference signals (pilots).
Figure 7 LTE OFDMA MIMO VSA demodulation results.
The VSA demodulation results are shown in Figure 7. The constellation is shown in the upper left, showing the 16 QAM constellation for the physical downlink shared channel (PDSCH), as well as sync and control channels. The various channels being measured, their modulation formats and individual EVMs are shown in the frame summary table on the lower left of the figure.
The error summary, on the upper right of the figure, shows the composite EVM of approximately 0.96 percent measured on the FPGA development board with D/A converters. The MIMO information table, on the lower right, shows information about the orthogonal reference signals (pilots), antenna cross-talk and timing error.
This same test setup with the digital oscilloscope and VSA software can also be used to perform MIMO measurements on multi-channel RF transmitters, where crosstalk and cross-coupling between antenna channels may be critical. In addition, other RF impairments such as LO phase noise and power amplifier gain compression and phase distortion at various stages in the IF/RF up-converter chain could be evaluated with this test setup.
Mixed-signal SDRs present system-level integration testing challenges for the system engineer. Waveform impairments can be an accumulation of mixed-signal impairments occurring in the FPGA implementation, D/A converter, IF/RF up-converter and power amplifier. MIMO can further add to the test and debug complexities with multiple IF/RF transmit chains and antennas. Using VSA software on both a logic analyzer and a digital oscilloscope enables the engineer to probe along the mixed-signal SDR chain to isolate issues and gain insight into where waveform impairments are occurring. The logic analyzer’s FPGA dynamic probe capability adds another level of debugging capability by enabling SDR FPGA engineers to select various internal FPGA signal banks to evaluate the design with the VSA software at various probe points in the implementation. The continuity provided with the VSA software on both a logic analyzer and a digital oscilloscope provides the system engineer with a powerful cross-domain analysis tool to gain insight into the mixed-signal SDR performance, whether it is digital baseband, analog IF/RF, or both.
“Mobile WiMAX” is a registered trademark of the WiMAX Forum.
- LTE and the Evolution to 4G Wireless: Design and Measurement Challenges, Moray Rumney, Ed., Agilent Technologies, 2009, ISBN 978-988-17935-1-5.
- “Solutions for MIMO RF Test and Debug—Ensuring Quick and Accurate Four-channel, Phase-coherent MIMO Measurements,” Application Note, www.agilent.com/find/powerofx.
Greg Jue is an applications development engineer/scientist with Agilent’s High Performance Scopes team. Previously, he was with Agilent EEsof Electronic Design Automation (EDA), specializing in SDR, LTE and WiMAX™ applications. He wrote the design simulation section in Agilent’s new LTE book and has authored numerous articles, presentations and application notes, including Agilent’s LTE algorithm reference whitepaper and Agilent’s new Cognitive Radio whitepaper. Before joining Agilent in 1995, he worked on system design for the Deep Space Network at the Jet Propulsion Laboratory at Caltech University.
Brad Frieden received his MSEE degree from the University of Texas at Austin. He is a logic and protocol analyzer applications specialist with Agilent’s Digital Debug Solutions team. He has specialized in FPGA measurements with the FPGA Dynamic Probe and written a variety of articles on this topic and other logic analyzer applications.