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The PCI-SIG® recently released Revision 3.0 of the PCIe base specification. Many changes in the physical-layer specification are related to ensuring proper bit transmission at 8 GT/s over inexpensive PC boards. Receiver tests are normative now; in previous versions of the standard, these tests were merely informative.
Devices operating at 8 GT/s present new measurement challenges that require new tools and procedures to accurately validate receiver design. These challenges include optimizing transmit and receive equalization, calibration channel design and device link training with 128/130-bit coded pattern sequences. One of the most challenging requirements is implementing a new procedure for calibrating PCIe 3.0 stress conditions as a reference receiver would see them after applied equalization. The procedure requires engineers to post-process signals measured at an accessible test point.
Agilent's complete and accurate PCIe 3.0 receiver test solution is based on the J-BERT N4903B high-performance serial BERT, the N4916B de-emphasis signal converter, the 81150A pulse function arbitrary noise generator, an Infiniium 90000 X-Series high-performance oscilloscope, new accessories and new N5990A test automation software.
Benefits of the Agilent PCIe 3.0 receiver characterization solution include:
*accurate and repeatable receiver test results enabled by new stress calibration software, adjustable pre- and post-cursor de-emphasis, J-BERT's built-in PCIe 3.0-compliant jitter and sinusoidal interference sources, new PJ sweep functionality and new PCIe 3.0-compliant calibration channels;
*higher R&D efficiency enabled by the new PCIe 3.0 stress calibration software and the new PCIe 3.0 link-training wizard, which controls J-BERT's pattern sequencer to bring the device under test into loopback mode; and investment protection enabled by using Agilent instruments that can be repurposed for accurate characterization for multiple gigabit test applications, such as USB3, SATA3, and QPI.
"Agilent's new PCIe 3.0 receiver tolerance test solution fills a critical need of ASIC and chipset designers for rolling out the next generation of PCI Express smoothly," said J�rgen Beck, general manager of Agilent's Digital Photonic Test Division. "By adding our expertise in accurate stress calibration and receiver tolerancing, we continue to help R&D teams efficiently release robust, next-generation chipsets for the computer industry."
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